# US 8,772,878 B2 · Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,878 B2 - Document ID: US8772878B2 - Status: Granted - Kind: B2 - Application number: 13/362,763 - Filed: 2012-01-31 - Published: 2012-05-24 - Granted: 2014-07-08 - Earliest claimed: 2008-07-31 - Assignees: Globalfoundries Inc. - Applicants: Jan Hoentschel; Vassilios Papageorgiou; Belinda Hannon - Inventors: Jan Hoentschel; Vassilios Papageorgiou; Belinda Hannon - Web page: https://patentgrep.com/patent/US8772878B2 ## CPC - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 30/792: {comprising applied insulating layers, e.g. stress liners} - H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 62/8325: {Silicon carbide} - H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 84/0167: {Manufacturing their channels} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 86/01: Manufacture or treatment - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10P 30/204: {into Group IV semiconductors} - H10P 30/208: {of electrically inactive species} - H10P 30/21: {of electrically active species} - H10P 30/28: characterised by an annealing step, e.g. for activation of dopants - H10D 30/0212: {using self-aligned silicidation} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished. ## Claims ### Claim 1 A method, comprising: forming a plurality of first cavities adjacent to a first gate electrode structure of a first transistor and a plurality of second cavities adjacent to a second gate electrode structure of a second transistor, said first and second transistors being of different conductivity type; forming a semiconductor material in said pluralities of first and second cavities, said semiconductor material having a first type of strain; creating lattice damage in said semiconductor material selectively in said first transistor to form a substantially relaxed semiconductor material in said plurality of first cavities of said first transistor; forming a substantially continuous strain-inducing material layer above said first transistor, said substantially continuous strain-inducing material layer continuously covering substantially all exposed surfaces of said first transistor; and annealing said substantially relaxed semiconductor material in the presence of said substantially continuous strain-inducing material layer to re-crystallize said substantially relaxed semiconductor material in said plurality of first cavities of said first transistor into a strained state, said strained state corresponding to a second type of strain that is opposite to said first type of strain. ### Claim 2 (depends on 1) The method of claim 1, wherein said semiconductor material comprises a silicon/carbon alloy. ### Claim 3 (depends on 1) The method of claim 1, wherein said pluralities of first and second cavities are formed in a common etch process. ### Claim 4 (depends on 1) The method of claim 1, further comprising forming a first strain-inducing layer above metal silicide regions of said first transistor and forming a second strain-inducing layer on metal silicide regions of said second transistor, wherein said first and second strain-inducing layers generate a different type of strain. ### Claim 5 (depends on 1) The method of claim 1, further comprising forming spacer elements adjacent to sidewalls of at least one of said first and second gate electrode structures prior to forming said first and second cavities. ### Claim 6 (depends on 5) The method of claim 5, further comprising removing said sidewall spacer elements from said sidewalls of said at least one of said first and second gate electrode structures after forming said pluralities of first and second cavities. ### Claim 7 (depends on 1) The method of claim 1, wherein creating said lattice damage in said semiconductor material selectively in said first transistor comprises forming a patterned mask layer to cover said second transistor and expose said first transistor and thereafter performing an ion bombardment process on said semiconductor material in said plurality of first cavities of said first transistor. ### Claim 8 (depends on 7) The method of claim 7, wherein said first gate electrode structure comprises a cap layer, said cap layer acting as a mask during said ion bombardment process. ### Claim 9 (depends on 1) The method of claim 1, further comprising removing said substantially continuous strain-inducing material layer from above said first transistor after annealing said substantially relaxed semiconductor material. ### Claim 10 A method, comprising: forming a first gate electrode structure of a first transistor and a second gate electrode structure of a second transistor above a semiconductor layer of a semiconductor device, said first gate electrode structure comprising a first cap layer and said second gate electrode structures comprising a second cap layer; forming a plurality of first cavities and a plurality of second cavities in said semiconductor layer adjacent to sidewalls of said first and second gate electrodes, respectively, using said first and second cap layers, respectively, as masks; forming a semiconductor material in said pluralities of first and second cavities, said semiconductor material having a first type of strain; after forming said semiconductor material in said pluralities of first and second cavities, forming a substantially continuous strain-inducing material layer above said first transistor, said substantially continuous strain-inducing material layer continuously covering substantially all exposed surfaces of said first transistor; and selectively changing said strain of said semiconductor material formed in said plurality of first cavities from said first type of strain to a second type of strain that is of an opposite type to said first type of strain, wherein selectively changing said strain of said semiconductor material in said plurality of first cavities comprises performing an annealing process in the presence of said substantially continuous strain-inducing material layer. ### Claim 11 (depends on 10) The method of claim 10, wherein selectively changing said strain of said semiconductor material in said plurality of first cavities from said first type of strain to said second type of strain further comprises forming a mask layer above said semiconductor device so as to cover said second transistor and to expose said first transistor, and thereafter performing an ion bombardment process on said semiconductor material in said plurality of first cavities. ### Claim 12 (depends on 11) The method of claim 11, further comprising removing said first cap layer from said first gate electrode structure prior to performing said ion bombardment process. ### Claim 13 (depends on 10) The method of claim 10, further comprising forming offset spacer elements adjacent to sidewalls of said first and second gate electrode structures and using said offset spacer elements as masks to form said pluralities of first and second cavities. ### Claim 14 (depends on 10) The method of claim 10, wherein said first and second cavities are formed in said semiconductor layer during a common etch process. ### Claim 15 (depends on 10) The method of claim 10, further comprising forming a further strain-inducing material layer above at least one of said first and second transistors after selectively changing said strain of said semiconductor material from said first type of strain to said second type of strain. ### Claim 16 (depends on 10) The method of claim 10, wherein forming said substantially continuous strain-inducing material layer above said first transistor comprises forming said substantially continuous strain-inducing material layer above said second transistor such that said substantially continuous strain-inducing material layer continuously covers substantially all exposed surfaces of said second transistor. ### Claim 17 (depends on 11) The method of claim 11, wherein said ion bombardment process is performed prior to forming said substantially continuous strain-inducing material layer. ### Claim 18 (depends on 4) The method of claim 4, further comprising removing said substantially continuous strain-inducing material layer from above said first transistor prior to forming said first strain-inducing layer. ### Claim 19 (depends on 18) The method of claim 18, further comprising forming an etch stop layer above said first transistor prior to forming said substantially continuous strain-inducing material layer and using said etch stop layer to remove said substantially continuous strain-inducing material layer. ### Claim 20 A method, comprising: forming a plurality of first cavities adjacent to a first gate electrode structure of a first transistor and a plurality of second cavities adjacent to a second gate electrode structure of a second transistor, said first and second transistors being of different conductivity type; forming a semiconductor material in said first and second cavities, said semiconductor material having a first type of strain; creating lattice damage in said semiconductor material selectively in said first transistor to form a substantially relaxed semiconductor material in said plurality of first cavities of said first transistor; forming a strain-inducing material layer above said first transistor; annealing said substantially relaxed semiconductor material in the presence of said strain-inducing material layer to re-crystallize said substantially relaxed semiconductor material in said plurality of first cavities of said first transistor into a strained state, said strained state corresponding to a second type of strain that is opposite to said first type of strain; removing said strain-inducing material from above said first transistor; and after removing strain-inducing material from above said first transistor, forming a first strain-inducing layer above metal silicide regions of said first transistor and forming a second strain-inducing layer on metal silicide regions of said second transistor, wherein said first and second strain-inducing layers generate a different type of strain. ### Claim 21 (depends on 16) The method of claim 16, further comprising removing said substantially continuous strain-inducing material layer from above said first and second transistors after performing said annealing process.