# US 8,772,877 B2 · Tunnel field-effect transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,877 B2 - Document ID: US8772877B2 - Status: Granted - Kind: B2 - Application number: 13/551,785 - Filed: 2012-07-18 - Published: 2013-01-24 - Granted: 2014-07-08 - Earliest claimed: 2011-07-22 - Assignees: International Business Machines Corporation - Applicants: Mikael T Bjoerk; Andreas Christian Doering; Phillip Stanley-Marbell; Kirsten Emilie Moselund - Inventors: Mikael T Bjoerk; Andreas Christian Doering; Phillip Stanley-Marbell; Kirsten Emilie Moselund - Web page: https://patentgrep.com/patent/US8772877B2 ## CPC - H10D 12/211: {Gated diodes} - H10D 64/311: {Gate electrodes for field-effect devices} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region. ## Claims ### Claim 1 A tunnel field-effect transistor, comprising: at least a source region comprising a corresponding source semiconductor material; at least a drain region comprising a corresponding drain semiconductor material; and at least a channel region comprising a corresponding channel semiconductor material, which is arranged between and in contact with said source region and said drain region, said tunnel field-effect transistor further comprising: at least a source-channel gate electrode provided on top of and overlapping at least an interface between said source region and said channel region; at least an insulator corresponding to said source-channel gate electrode that is provided between said source-channel gate electrode and at least said interface between said source region and said channel region; at least a drain-channel gate electrode provided on top of and overlapping at least an interface between said drain region and said channel region; and at least an insulator corresponding to said drain-channel gate electrode that is provided between said drain-channel gate electrode and at least said interface between said drain region and said channel region. ### Claim 2 (depends on 1) The tunnel field-effect transistor according to claim 1, wherein said source-channel gate electrode is configurable to control a tunnelling current that flows between a tunnelling junction formed at said interface between said source region and said channel region and said drain-channel gate electrode is configurable to control a tunnelling current that flows between a tunnelling junction formed at said interface between said drain region and said channel region. ### Claim 3 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein said tunnelling field-effect transistor is configurable to implement at least one of: an XNOR logic gate and an XOR logic gate. ### Claim 4 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein a distance between said source-channel gate electrode and said drain-channel gate electrode is chosen such that said tunnel field-effect transistor is operable in one of an on mode and an off mode. ### Claim 5 (depends on 4) The tunnel field-effect transistor according to claim 4, wherein said distance between said source-channel gate electrode and said drain-channel gate electrode is chosen to be in the 10-100 nm range. ### Claim 6 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein said tunnelling field-effect transistor is implemented in one of: a planar film, a vertically-standing two-dimensional layer, a nanowire geometry, and a tubular configuration. ### Claim 7 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein said source semiconductor material is chosen to be different from at least said drain semiconductor material. ### Claim 8 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein said source semiconductor material, said channel semiconductor material and said drain semiconductor material are chosen to be the same. ### Claim 9 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein said source semiconductor material, said channel semiconductor material and said drain semiconductor material are chosen to be different from each other. ### Claim 10 (depends on 2) The tunnel field-effect transistor according to claim 2, wherein a respective doping profile of said source semiconductor material and said drain semiconductor material are chosen to facilitate manipulation of a respective electrical field established at said interface between said source region and said channel region, and said interface between said drain region and said channel region. ### Claim 11 (depends on 2) The tunnel field-effect transistor according to claim 2, further comprising a strain applicator that is configurable to apply a strain to at least one of: said interface between said source region and said channel region; and said interface between said drain region and said channel region. ### Claim 12 A method for fabricating a tunnel field-effect transistor, comprising: providing at least a source region comprising a corresponding source semiconductor material; providing at least a drain region comprising a corresponding drain semiconductor material; and providing at least a channel region comprising a corresponding channel semiconductor material, which is arranged between and in contact with said source region and said drain region, said method further comprising: providing at least a source-channel gate electrode on top of and overlapping at least an interface between said source region and said channel region; providing at least an insulator corresponding to said source-channel gate electrode between said source-channel gate electrode and at least said interface between said source region and said channel region; providing at least a drain-channel gate electrode on top of and overlapping at least an interface between said drain region and said channel region; and providing at least an insulator corresponding to said drain-channel gate electrode between said drain-channel gate electrode and at least said interface between said drain region and said channel region. ### Claim 13 (depends on 12) The method according to claim 12 further comprising: configuring said source-channel gate electrode to control a tunnelling current that flows between a tunnelling junction formed at said interface between said source region and said channel region; and configuring said drain-channel gate electrode to control a tunnelling current that flows between a tunnelling junction formed at said interface between said drain region and said channel region. ### Claim 14 (depends on 13) The method according to claim 13, further comprising the step of implementing at least one of: an XNOR logic gate and an XOR logic gate. ### Claim 15 (depends on 13) The method according to claim 13, further comprising: selecting a distance between said source-channel gate electrode and said drain-channel gate electrode such that said tunnel field-effect transistor is operable in one of an on mode and an off mode. ### Claim 16 (depends on 15) The method according to claim 15, wherein said distance between said source-channel gate electrode and said drain-channel gate electrode is selected to be in the 10-100 nm range. ### Claim 17 (depends on 13) The method according to claim 13, further comprising the step of implementing said tunnel field-effect transistor in one of: a planar film, a vertically-standing two-dimensional layer, a nanowire geometry, and a tubular configuration. ### Claim 18 (depends on 13) The method according to claim 13, further comprising selecting said source semiconductor material to be different from at least said drain semiconductor material. ### Claim 19 (depends on 13) The method according to claim 13, further comprising selecting said source semiconductor material, said channel semiconductor material and said drain semiconductor material to be the same. ### Claim 20 (depends on 13) The method according to claim 13, further comprising selecting said source semiconductor material, said channel semiconductor material and said drain semiconductor material to be different from each other. ### Claim 21 (depends on 13) The method according to claim 13, further comprising selecting a respective doping profile of said source semiconductor material and said drain semiconductor material, thereby facilitating manipulation of a respective electrical field established at said interface between said source region and said channel region, and said interface between said drain region and said channel region. ### Claim 22 (depends on 13) The method according to claim 13, further comprising providing a strain applicator that is configurable to apply a strain to at least one of: said interface between said source region and said channel region; and said interface between said drain region and said channel region. ### Claim 23 (depends on 1) A method of implementing an XNOR logic gate, the method comprising: using a tunnel field-effect transistor according to claim 1.