# US 8,772,876 B2 · High-voltage silicon-on-insulator transistors and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,876 B2 - Document ID: US8772876B2 - Status: Granted - Kind: B2 - Application number: 11/929,694 - Filed: 2007-10-30 - Published: 2008-02-28 - Granted: 2014-07-08 - Earliest claimed: 2006-02-03 - Assignees: International Business Machines Corporation - Applicants: William Hsioh-Lien Ma; Jack Allan Mandelman; Carl John Radens; William Robert Tonti - Inventors: William Hsioh-Lien Ma; Jack Allan Mandelman; Carl John Radens; William Robert Tonti - Web page: https://patentgrep.com/patent/US8772876B2 ## CPC - H10D 30/0323: {comprising monocrystalline silicon} - H10D 30/6708: {for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect} - H10D 30/6717: {the source and the drain regions being asymmetrical} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided. ## Claims ### Claim 1 A high-voltage transistor, comprising: a gate channel formed in a silicon-on-insulator (SOI) layer of a substrate, wherein the substrate includes a bulk silicon layer that is below an insulator layer that is below the SOI layer; a first transistor node coupled to the gate channel; and a second transistor node coupled to the gate channel; wherein: the first transistor node includes a first diffusion region of the transistor, and a portion of the first transistor node is formed in the SOI layer; a portion of the first transistor node includes a first epitaxial silicon layer formed on the first diffusion region, and the first diffusion region and the first epitaxial silicon layer have a combined first resistance sufficient to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V; the second transistor node includes a second diffusion region of the transistor, and a portion of the second transistor node is formed in the SOI layer; and a portion of the second transistor node includes a second epitaxial silicon layer formed on the second diffusion region, and the second diffusion region and the second epitaxial silicon layer have a combined second resistance lower than the first resistance such that a negligible voltage drop occurs across the second transistor node. ### Claim 2 (depends on 1) The high-voltage transistor of claim 1 further comprising an insulating spacer on a portion of the first diffusion region; wherein a resistance of a portion of the first diffusion region covered by the spacer is higher than a resistance of a portion of the first diffusion region not covered by the spacer. ### Claim 3 (depends on 2) The high-voltage transistor of claim 2 wherein the insulating spacer is about 10 nm to about 100 nm wide. ### Claim 4 (depends on 2) The high-voltage transistor of claim 2 wherein a thickness of silicon in the first diffusion region is between about 10 nm and about 100 nm. ### Claim 5 (depends on 1) The high-voltage transistor of claim 1 further comprising: an insulating spacer formed on a portion of the first diffusion region; wherein the first diffusion region has a dopant concentration in the range of 1×1015 cm−3 to 1×1017 cm−3 and the first epitaxial silicon layer has a dopant concentration in the range of 1×1018 cm−3 to 1×1020 cm−3. ### Claim 6 (depends on 5) The high-voltage transistor of claim 5 wherein the insulating spacer is about 5 nm to about 200 nm wide. ### Claim 7 (depends on 5) The high-voltage transistor of claim 5 wherein the first epitaxial silicon layer is about 10 nm to about 100 nm thick. ### Claim 8 (depends on 5) The high-voltage transistor of claim 5 wherein a resistance of the first epitaxial layer is less than a resistance of the first diffusion region. ### Claim 9 (depends on 1) The high-voltage transistor of claim 1, wherein the first epitaxial silicon layer further has a dimension sufficient to reduce the voltage greater than about 5 V within the transistor to a voltage less than about 3 V. ### Claim 10 A substrate, comprising: a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and a high-voltage transistor, comprising: a gate channel formed in the SOI layer of the substrate; a first transistor node coupled to the gate channel; and a second transistor node coupled to the gate channel; wherein: the first transistor node includes a first diffusion region of the transistor, and a portion of the first transistor node is formed in the SOI layer; a portion of the first transistor node includes a spacer formed on a portion of the first diffusion region, wherein the spacer covers a portion of the first diffusion region, the covered portion of the first diffusion region having a lower dopant concentration than an uncovered portion of the first diffusion region, wherein the covered portion has a dopant concentration sufficient to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V; and the second transistor node includes a second diffusion region of the transistor, and a portion of the second transistor node is formed in the SOI layer, the covered portion of the first diffusion region having a lower dopant concentration than the second diffusion region. ### Claim 11 (depends on 10) The substrate of claim 10 wherein the resistance of the covered portion of the first diffusion region is higher than a resistance of the uncovered portion of the first diffusion region, and the resistance of the covered portion is sufficient to reduce the voltage greater than about 5 V within the transistor to a voltage less than about 3 V. ### Claim 12 (depends on 10) The substrate of claim 10, wherein the covered portion of the first diffusion region further has a dimension sufficient to reduce the voltage greater than about 5 V within the transistor to a voltage less than about 3 V. ### Claim 13 (depends on 10) The substrate of claim 10, wherein the spacer has a width of about 80 nm to about 200 nm. ### Claim 14 (depends on 10) The substrate of claim 10, wherein the dopant concentration of the covered portion is about 1×1015 cm−3 to about 1×1017 cm−3.