# US 8,772,873 B2 · Ge-on-insulator structure and method for forming the same

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- Number: US 8,772,873 B2
- Document ID: US8772873B2
- Status: Granted
- Kind: B2
- Application number: 13/201,903
- Filed: 2011-07-27
- Published: 2012-07-26
- Granted: 2014-07-08
- Earliest claimed: 2011-01-24
- Assignees: Tsinghua University
- Applicants: Jing Wang; Jun Xu; Lei Guo
- Inventors: Jing Wang; Jun Xu; Lei Guo
- Web page: https://patentgrep.com/patent/US8772873B2

## CPC

- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10P 90/1922: {using silicon etch back techniques, e.g. BESOI or ELTRAN}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.

## Claims

### Claim 1

A method for forming a Ge-on-insulator structure, comprising steps of:
forming a Ge layer on a substrate;
treating a first surface of the Ge layer to form a first semiconducting metal-germanide passivation layer;
bonding the first semiconducting metal-germanide passivation layer with a silicon substrate, wherein on a surface of the silicon substrate an oxide insulating layer is formed; and
removing the substrate.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
after the substrate is removed, treating a second surface of the Ge layer to form a second semiconducting metal-germanide passivation layer.

### Claim 3 (depends on 2)

The method according to claim 2, further comprising:
forming a gate dielectric layer on the second semiconducting metal-germanide passivation layer;
forming a gate electrode on the gate dielectric layer; and
forming a source and a drain in the Ge layer.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
after the substrate is removed, treating a second surface of the Ge layer to form a Ge1-xSix passivation layer, wherein x is within a range from 0 to 1.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the metal is at least one metal selected from a group consisting of strontium, barium or stannum.

### Claim 6 (depends on 2)

The method according to claim 2, wherein the metal is at least one metal selected from a group consisting of strontium, barium or stannum.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the Ge layer is a strained Ge layer, a strained Ge1-ySiy layer, a relaxed Ge layer or a relaxed Ge1-ySiy layer, wherein y is within a range from 0 to 1.

### Claim 8

A Ge-on-insulator structure, comprising:
a silicon substrate, wherein on a surface of the silicon substrate an oxide insulating layer is formed; and
a Ge layer formed on the silicon substrate,
wherein a first semiconducting metal-germanide passivation layer is formed between the Ge layer and the silicon substrate.

### Claim 9 (depends on 8)

The Ge-on-insulator structure according to claim 8, further comprising:
a second semiconducting metal-germanide passivation layer formed on the Ge layer.

### Claim 10 (depends on 9)

The Ge-on-insulator structure according to claim 9, further comprising:
a gate dielectric layer formed on the second semiconducting metal-germanide passivation layer,
a gate electrode formed on the gate dielectric layer; and
a source and a drain formed in the Ge layer.

### Claim 11 (depends on 8)

The Ge-on-insulator structure according to claim 8, further comprising:
a Ge1-xSix passivation layer formed on the Ge layer, wherein x is within a range from 0 to 1.

### Claim 12 (depends on 8)

The Ge-on-insulator structure according to claim 8, wherein the metal is at least one metal selected from a group consisting of strontium, barium or stannum.

### Claim 13 (depends on 9)

The Ge-on-insulator structure according to claim 9, wherein the metal is at least one metal selected from a group consisting of strontium, barium or stannum.

### Claim 14 (depends on 8)

The Ge-on-insulator structure according to claim 8, wherein the Ge layer is a strained Ge layer, a strained Ge1-ySiy layer, a relaxed Ge layer or a relaxed Ge1-ySiy layer, wherein y is within a range from 0 to 1.