# US 8,772,867 B2 · High voltage high side DMOS and the method for forming thereof

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- Number: US 8,772,867 B2
- Document ID: US8772867B2
- Status: Granted
- Kind: B2
- Application number: 13/692,984
- Filed: 2012-12-03
- Published: 2014-06-05
- Granted: 2014-07-08
- Earliest claimed: 2012-12-03
- Applicants: Monolithic Power Systems, Inc.
- Inventors: Ji-Hyoung Yoo; Martin E. Garnett
- Web page: https://patentgrep.com/patent/US8772867B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.

## Claims

### Claim 1

A high voltage high side DMOS, comprising:
a P-type substrate with an epitaxial layer formed on the P-type substrate;
a field oxide formed on the epitaxial layer;
an N-type well region formed in the epitaxial layer;
a gate oxide formed on the epitaxial layer;
a gate poly formed on the gate oxide and on the field oxide;
a P-type base region formed in the epitaxial layer;
a deep P-type region merging with the P-type base region formed in the epitaxial layer;
an N-type lightly doped well region formed under the P-type base region in the epitaxial layer, wherein the N-type well region is formed in the N-type lightly doped well region;
a first N-type highly doped region formed in the N-type well region;
a second N-type highly doped region formed in the P-type base region;
a P-type highly doped region formed in the P-type base region, the P-type highly doped region being adjacent to the second N-type highly doped region;
a TEOS layer formed on the gate poly;
an inter layer dielectric formed on the TEOS layer and on the gate oxide;
a drain electrode contacted with the first N-type highly doped region; and
a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.

### Claim 2 (depends on 1)

The high voltage high side DMOS of claim 1, wherein the TEOS layer has a thickness around 500 Å.

### Claim 3 (depends on 1)

The high voltage high side DMOS of claim 1, wherein the deep P-type region has a dose in the range of 1*1013 cm-3 to 1*1015 cm-3, and has an implant energy around 100 keV.

### Claim 4 (depends on 1)

The high voltage high side DMOS of claim 1, wherein
the space from the edge of the P-type base region to the edge of the N-type well region is around 0.8 μm; and
the space from the edge of the N-type well region to the edge of the first N-type highly doped region is around 2.5 μm.

### Claim 5 (depends on 1)

The high voltage high side DMOS of claim 1, wherein the combined junction of the P-type base region and the deep P-type region is round, and has a curvature larger than 0.5 μm.

### Claim 6

A method for forming a high voltage high side DMOS, comprising:
forming an epitaxial layer on a substrate;
forming a field oxide and an N-type well region in the epitaxial layer;
forming a gate oxide on the epitaxial layer;
forming a gate poly on the gate oxide and on the field oxide;
forming a TEOS layer on the gate poly;
forming a P-type base region in the epitaxial layer;
forming a deep P-type region merging with the P-type base region in the epitaxial layer;
forming a first N-type highly doped region in the N-type well region, forming a second N-type highly doped region and a P-type highly doped region adjacent to the second N-type highly doped region in the P-type base region;
forming an inter layer dielectric on the TEOS layer and on the gate oxide;
forming a drain electrode contacted with the first N-type highly doped region, and forming a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.

### Claim 7 (depends on 6)

The method of claim 6, further comprising: forming an N-type lightly doped well region in the epitaxial layer before the formation of the N-type well region, wherein the N-type well region is formed in the N-type lightly doped well region.

### Claim 8 (depends on 6)

The method of claim 6, wherein the deep P-type region has a dose in the range of 1*1013 cm-3 to 1*1015 cm-3, and has an implant energy around 100 keV.

### Claim 9 (depends on 6)

The method of claim 6, wherein the combined junction of the P-type base region and the deep P-type region is round, and has a curvature larger than 0.5 μm.

### Claim 10 (depends on 6)

The method of claim 6, wherein
the space from the edge of the P-type base region to the edge of the N-type well region is around 0.8 μm; and
the space from the edge of the N-type well region to the edge of the first N-type highly doped region is around 2.5 μm.

### Claim 11

A high voltage high side DMOS, comprising:
a P-type substrate with an epitaxial layer formed on the P-type substrate;
a field oxide formed on the epitaxial layer;
an N-type well region formed in the epitaxial layer;
a gate oxide formed on the epitaxial layer;
a gate poly formed on the gate oxide and on the field oxide;
a P-type base region formed in the epitaxial layer;
a first N-type highly doped region formed in the N-type well region;
a second N-type highly doped region formed in the P-type base region;
a P-type highly doped region formed in the P-type base region, the P-type highly doped region being adjacent to the second N-type highly doped region;
a TEOS layer formed on the gate poly;
an inter layer dielectric formed on the TEOS layer and on the gate oxide;
a drain electrode contacted with the first N-type highly doped region; and
a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.

### Claim 12 (depends on 11)

The high voltage high side DMOS of claim 11, further comprising: a deep P-type region merging with the P-type base region formed in the epitaxial layer.

### Claim 13 (depends on 11)

The high voltage high side DMOS of claim 11, further comprising: an N-type lightly doped well region formed under the P-type base region in the epitaxial layer.

### Claim 14 (depends on 11)

The high voltage high side DMOS of claim 11, wherein the field oxide has a shallow-trench isolation structure.

### Claim 15 (depends on 11)

The high voltage high side DMOS of claim 11, wherein the high voltage high side DMOS is in an application where the potential difference between the P-type base region to the substrate is less than one volt.