# US 8,772,862 B2 · Semiconductor device and method for fabricating the same

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- Number: US 8,772,862 B2
- Document ID: US8772862B2
- Status: Granted
- Kind: B2
- Application number: 13/711,673
- Filed: 2012-12-12
- Published: 2014-01-23
- Granted: 2014-07-08
- Earliest claimed: 2012-07-17
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Heung-Jae Cho
- Web page: https://patentgrep.com/patent/US8772862B2

## CPC

- H10D 62/8325: {Silicon carbide}
- H10B 12/05: {Making the transistor}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.

## Claims

### Claim 1

A vertical channel transistor comprising:
a pillar formed over a substrate; and
a gate electrode formed on sidewalls of the pillar,
wherein the pillar comprises a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.

### Claim 2 (depends on 1)

The vertical channel transistor of claim 1, wherein the leakage prevention area comprises a layer containing carbon (C).

### Claim 3 (depends on 1)

The vertical channel transistor of claim 1, wherein the leakage prevention area comprises silicon carbide (SiC).

### Claim 4 (depends on 1)

The vertical channel transistor of claim 1, wherein the drain area comprises silicon.

### Claim 5 (depends on 1)

The vertical channel transistor of claim 1, wherein the drain area comprises single crystalline silicon.

### Claim 6

A method for fabricating a vertical channel transistor, comprising:
forming a pillar over a substrate; and
forming a gate electrode on sidewalls of the pillar,
wherein the pillar comprises a source area, a vertical channel area over the source area, a leakage prevention area over the vertical channel area, and a drain area.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming of the pillar comprises:
forming a pillar pattern by etching the substrate;
forming a leakage prevention area at an upper part of the pillar pattern;
forming a silicon layer over the leakage prevention area; and
forming a drain area and a source area by ion-implanting impurities into the silicon layer and a lower part of the pillar pattern.

### Claim 8 (depends on 7)

The method of claim 7, wherein the forming of the leakage prevention area comprises performing ion implantation with a target set to a predetermined depth from the surface of the pillar pattern.

### Claim 9 (depends on 7)

The method of claim 7, wherein the forming of the leakage prevention area comprises performing ion implantation on the surface of the pillar pattern.

### Claim 10 (depends on 7)

The method of claim 7, wherein the forming of the leakage prevention area comprises performing epitaxial growth over the pillar pattern.

### Claim 11 (depends on 7)

The method of claim 7, wherein the forming of the silicon layer comprises performing epitaxial growth over the leakage prevention area.

### Claim 12 (depends on 6)

The method of claim 6, wherein the forming of the pillar comprises:
forming a leakage prevention area over the substrate;
forming a silicon layer over the leakage prevention area;
forming the pillar by etching the leakage prevention area, the silicon layer, and the substrate; and
forming a drain area and a source area by ion-implanting impurities into the silicon layer and a lower part of the pillar.

### Claim 13 (depends on 12)

The method of claim 12, wherein the forming of the leakage prevention area comprises performing ion implantation with a target set to a predetermined depth from the substrate surface.

### Claim 14 (depends on 12)

The method of claim 12, wherein the forming of the leakage prevention area comprises performing ion implantation on the substrate surface.

### Claim 15 (depends on 12)

The method of claim 12, wherein the forming of the leakage prevention area comprises performing epitaxial growth on the substrate.

### Claim 16 (depends on 12)

The method of claim 12, wherein the forming of the silicon layer comprises performing epitaxial growth on the leakage prevention area.

### Claim 17 (depends on 6)

The method of claim 6, wherein the leakage prevention area comprises a layer containing carbon.

### Claim 18 (depends on 6)

The method of claim 6, wherein the leakage prevention area comprises SiC.

### Claim 19

A semiconductor device comprises:
a pillar formed over a substrate including a buried bit line;
a gate electrode formed on sidewalls of the pillar; and
a capacitor connected to a drain area of the pillar,
wherein the pillar comprises a source area connected to the buried bit line, a vertical channel area over the source area, a leakage prevention area over the vertical channel area, and a drain area over the leakage prevention area.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the leakage prevention area comprises a layer containing carbon.

### Claim 21 (depends on 19)

The semiconductor device of claim 19, wherein the leakage prevention area comprises SiC.