# US 8,772,856 B2 · Charge storage nodes with conductive nanodots

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- Number: US 8,772,856 B2
- Document ID: US8772856B2
- Status: Granted
- Kind: B2
- Application number: 12/693,062
- Filed: 2010-01-25
- Published: 2011-07-28
- Granted: 2014-07-08
- Earliest claimed: 2010-01-25
- Assignees: Micron Technology, Inc.
- Applicants: Nirmal Ramaswamy
- Inventors: Nirmal Ramaswamy
- Web page: https://patentgrep.com/patent/US8772856B2

## CPC

- H10D 30/6893: {wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- Y10S 977/774: Exhibiting three-dimensional carrier confinement, e.g. quantum dots
- Y10S 977/943: Information storage or retrieval using nanostructure
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Memory cells formed to include a charge storage node having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems.

## Claims

### Claim 1

A memory cell, comprising:
a first dielectric over a semiconductor;
a charge storage node over the first dielectric;
a second dielectric over the charge storage node;
a control gate over the second dielectric; and
source/drain regions in the semiconductor generally adjacent the first dielectric;
wherein the charge storage node comprises a charge storage material and conductive nanodots; and
wherein the conductive nanodots are between the charge storage material and the second dielectric.

### Claim 2 (depends on 1)

The memory cell of claim 1, further comprising a barrier between the conductive nanodots and the charge storage material.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the conductive nanodots have a density of 1E12/cm2 to 1E15/cm2.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein the conductive nanodots comprise metal-containing nanodots.

### Claim 5 (depends on 4)

The memory cell of claim 4, wherein the metal-containing nanodots comprise at least one metal-containing material selected from the group consisting of elemental metals, metal alloys, metal nitrides and metal silicides.

### Claim 6 (depends on 5)

The memory cell of claim 5, wherein metals of the elemental metals, metal alloys, metal nitrides and metal silicides of the at least one metal-containing material are selected from the group consisting of titanium, tantalum, tungsten, ruthenium, rhodium, and platinum.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the charge storage material comprises a silicon-containing material.

### Claim 8 (depends on 7)

The memory cell of claim 7, wherein the silicon-containing material is selected from the group consisting of monocrystalline silicon, amorphous silicon and polycrystalline silicon, and wherein the silicon-containing material is either undoped or conductively doped.

### Claim 9 (depends on 7)

The memory cell of claim 7, further comprising a barrier between the charge storage material and the conductive nanodots, wherein the barrier comprises a dielectric material selected from the group consisting of an oxide, a nitride and an oxynitride.

### Claim 10

A memory cell, comprising:
a tunnel dielectric over a semiconductor;
a silicon-containing charge storage material over the tunnel dielectric;
a nitridized barrier over the silicon-containing charge storage material;
metal-containing nanodots over the nitridized barrier;
an intergate dielectric over the metal-containing nanodots;
a control gate over the intergate dielectric; and
source/drain regions in the semiconductor generally adjacent the tunnel dielectric.

### Claim 11 (depends on 10)

The memory cell of claim 10, wherein the silicon-containing charge storage material comprises polysilicon.

### Claim 12 (depends on 11)

The memory cell of claim 11, wherein the polysilicon is conductively doped.

### Claim 13 (depends on 10)

The memory cell of claim 10, wherein the metal-containing nanodots comprise at least one metal selected from the group consisting of titanium, tantalum, tungsten, ruthenium, rhodium, and platinum.

### Claim 14 (depends on 10)

The memory cell of claim 10, wherein the nitridized barrier comprises a silicon oxynitride.

### Claim 15 (depends on 10)

The memory cell of claim 10, wherein the silicon-containing charge storage material comprises polysilicon conductively doped to a p-type conductivity, wherein the nitridized barrier comprises a silicon oxynitride and wherein the metal-containing nanodots comprise elemental ruthenium.

### Claim 16 (depends on 15)

The memory cell of claim 15, wherein the metal-containing nanodots further comprise ruthenium silicide.

### Claim 17

A memory device, comprising:
an array of non-volatile memory cells; and
circuitry configured to control and/or access the array of non-volatile memory cells;
wherein at least one of the non-volatile memory cells comprises a charge storage node which comprises a charge storage material and conductive nanodots; and
wherein the conductive nanodots of the charge storage node are between the charge storage material and a control gate of the at least one of the non-volatile memory cells.

### Claim 18

A memory device, comprising:
an array of non-volatile memory cells; and
circuitry configured to control and/or access the array of non-volatile memory cells;
wherein at least one of the non-volatile memory cells comprises a charge storage node which comprises a charge storage material and conductive nanodots;
wherein the conductive nanodots of the charge storage node are between the charge storage material and a control gate of the at least one of the non-volatile memory cells;
wherein the charge storage node further comprises a barrier between the charge storage material and the conductive nanodots;
wherein the charge storage material is a silicon-containing material selected from the group consisting of undoped or conductively doped monocrystalline silicon, undoped or conductively doped amorphous silicon and undoped or conductively doped polycrystalline silicon;
wherein the barrier is a silicon-containing dielectric material selected from the group consisting of a silicon oxide, a silicon nitride and a silicon oxynitride;
wherein the conductive nanodots comprise metal-containing nanodots comprising at least one metal-containing material selected from the group consisting of elemental metals, metal alloys, metal nitrides and metal silicides; and
wherein metals of the elemental metals, metal alloys, metal nitrides and metal silicides of the at least one metal-containing material are selected from the group consisting of titanium, tantalum, tungsten, ruthenium, rhodium, and platinum.

### Claim 19

A memory device, comprising:
an array of non-volatile memory cells; and
circuitry configured to control and/or access the array of non-volatile memory cells;
wherein at least one of the memory cells comprises a gate stack having a tunnel dielectric over a semiconductor channel, a charge storage node over the tunnel dielectric, an intergate dielectric over the charge storage node and a control gate over the intergate dielectric, and wherein the charge storage node comprises a silicon-containing charge storage material, metal-containing nanodots and a silicon-containing barrier between the silicon-containing charge storage material and the metal-containing nanodots.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the silicon-containing charge storage material comprises a conductively-doped polycrystalline silicon, wherein the silicon-containing dielectric barrier comprises a silicon oxynitride and wherein the metal-containing nanodots comprise ruthenium.