# US 8,772,852 B2 · Nonvolatile memory devices including common source

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- Number: US 8,772,852 B2
- Document ID: US8772852B2
- Status: Granted
- Kind: B2
- Application number: 12/328,141
- Filed: 2008-12-04
- Published: 2009-06-11
- Granted: 2014-07-08
- Earliest claimed: 2007-12-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Hong-Soo Kim; Keon-Soo Kim
- Inventors: Hong-Soo Kim; Keon-Soo Kim
- Web page: https://patentgrep.com/patent/US8772852B2

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10B 41/10: characterised by the top-view layout
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 89/10: Integrated device layouts
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.

## Claims

### Claim 1

A nonvolatile memory device, comprising:
a device isolation pattern formed in a substrate, the device isolation pattern defining a plurality of first active regions and a second active region, wherein the plurality of first active regions extend in parallel to each other along a first direction, and wherein the second active region extends along a second direction perpendicular to the first direction and crosses the plurality of the first active regions, wherein the second active region is commonly connected to the plurality of the first active regions;
a common source formed in the second active region and extends along the second direction;
a plurality of common drains formed in the plurality of the first active regions, respectively;
a first selection line, a plurality of word lines, and a second selection line, each of the first selection line, the plurality of word lines, and the second selection line crossing the first active regions, each of the first selection line, the plurality of word lines, and the second selection line disposed between the common source and the common drains, and each of the first selection line, the plurality of word lines, and the second selection line in parallel to each other, wherein the common source has different conductive type than a channel region of one of the first selection line and the second selection line; and
a source conductive line disposed on the second active region, the source conductive line extending along the second direction and being electrically connected to the common source.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, further comprising a mold insulating layer which covers an entire surface of the substrate and includes a source groove exposing the common source,
wherein the source conductive line is disposed in the groove and connected to the common source.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein a top surface of the source conductive line is coplanar with a top surface of the mold insulating layer.

### Claim 4 (depends on 2)

The nonvolatile memory device of claim 2, further comprising:
an insulating interlayer disposed on the source conductive line and the mold insulating layer;
a plurality of bit line plugs respectively connected to the plurality of common drains by penetrating the insulating interlayer and the mold insulating layer; and
a plurality of bit lines which extend in parallel to each other along the first direction and are respectively connected to the plurality of common bit line plugs.

### Claim 5 (depends on 1)

The nonvolatile memory device of claim 1, further comprising:
a mold insulating layer covering an entire surface of the substrate; and
at least one contact plug connected to the common source through the mold insulating layer,
wherein the source conductive line is disposed on the mold insulating layer and is connected to the at least one contact plug.

### Claim 6 (depends on 5)

The nonvolatile memory device of claim 5, wherein the at least one contact plug is connected to the common source formed in a crossing region where the first active regions and the second active region cross each other.

### Claim 7 (depends on 6)

The nonvolatile memory device of claim 6, wherein a plurality of the contact plugs are disposed in the mold insulating layer,
the plurality of contact plugs are respectively connected to portions of the common sources formed at the crossing region where the plurality of first active regions cross the second active region, and
the plurality of the contact plugs are arranged in a row along the second direction.

### Claim 8 (depends on 5)

The nonvolatile memory device of claim 5, further comprising:
an insulating interlayer disposed on the source conductive line and the mold insulating layer;
a plurality of bit line plugs respectively connected to the plurality of common drains by penetrating the insulating interlayer and the mold insulating layer; and
a plurality of bit lines which extend in parallel to each other along the first direction and are respectively connected to the plurality of common bit line plugs.

### Claim 9 (depends on 1)

The nonvolatile memory device of claim 1, wherein the source conductive line includes a conductive material having lower resistivity than the common source.

### Claim 10 (depends on 1)

The nonvolatile memory device of claim 1, wherein the first selection line is disposed to be adjacent to the common source and the second selection line is disposed to be adjacent to the common drains.

### Claim 11 (depends on 10)

The nonvolatile memory device of claim 10, wherein the first selection line is spaced apart from the second active region in the first direction and the common source extends in the first active regions disposed between the second active region and the first selection line.

### Claim 12 (depends on 1)

The nonvolatile memory device of claim 1, further comprising cell source/drains formed in the first active regions of both sides of each of the word lines.

### Claim 13 (depends on 1)

The nonvolatile memory device of claim 1, wherein each of the word lines comprises:
a control gate electrode crossing one of the first active regions;
a charge storage layer interposed between the control gate electrode and the one of the first active regions;
a tunnel insulating layer interposed between the charge storage layer and the one of the first active regions; and
a blocking insulating layer interposed between the charge storage layer and the control gate electrode.

### Claim 14 (depends on 1)

The nonvolatile memory device of claim 1, wherein the common source is in a crossing region where the second active region crosses one of the first active regions.

### Claim 15

A nonvolatile memory device, comprising:
a device isolation pattern formed in a substrate, the device isolation pattern defining a plurality of first active regions and a second active region, wherein the plurality of first active regions extend in parallel to each other along a first direction, and wherein the second active region extends along a second direction perpendicular to the first direction and is commonly connected to the plurality of first active regions;
a common source formed in the second active region and extending along the second direction;
a plurality of common drains formed in the plurality of the first active regions, respectively; and
a plurality of word lines crossing the first active regions and extending along the second direction.

### Claim 16 (depends on 15)

The nonvolatile memory device of claim 15, wherein the common source and the common drains have different conductive type than the first active regions and the second active region.

### Claim 17 (depends on 15)

The nonvolatile memory device of claim 15, further comprising a first selection line adjacent the common source and crossing the first active regions, and a second selection line adjacent the common drains and crossing the first active regions.

### Claim 18 (depends on 17)

The nonvolatile memory device of claim 17, wherein the common source has different conductive type than a channel region of one of the first selection line and the second selection line.

### Claim 19 (depends on 17)

The nonvolatile memory device of claim 17, wherein the plurality of word lines are disposed between the first selection line and the second selection line.

### Claim 20 (depends on 15)

The nonvolatile memory device of claim 15, further comprising a source conductive line disposed on the second active region, the source conductive line extending along the second direction and being electrically connected to the common source.

### Claim 21 (depends on 20)

The nonvolatile memory device of claim 20, wherein the source conductive line directly contacts an entire upper surface of the common source.

### Claim 22 (depends on 20)

The nonvolatile memory device of claim 20, further comprising a mold insulating layer that covers an entire surface of the substrate and includes a source groove exposing the common source,
wherein the source conductive line is disposed in the source groove and connected to the common source.

### Claim 23 (depends on 20)

The nonvolatile memory device of claim 20, wherein the source conductive line includes a conductive material having lower resistivity than the common source.

### Claim 24 (depends on 15)

The nonvolatile memory device of claim 15, further comprising a plurality of bit lines that extend in parallel to each other along the first direction and are respectively connected to the plurality of common drains.