# US 8,772,849 B2 · Semiconductor memory device

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- Number: US 8,772,849 B2
- Document ID: US8772849B2
- Status: Granted
- Kind: B2
- Application number: 13/410,608
- Filed: 2012-03-02
- Published: 2012-09-13
- Granted: 2014-07-08
- Earliest claimed: 2011-03-10
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Kosei Noda
- Inventors: Kosei Noda
- Web page: https://patentgrep.com/patent/US8772849B2

## CPC

- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 1/68: Capacitors having no potential barriers
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween.

## Claims

### Claim 1

A semiconductor memory device comprising:
a semiconductor layer;
a first gate insulating layer over the semiconductor layer;
an insulating layer over the first gate insulating layer;
a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer;
a conductive layer provided in the insulating layer;
an oxide semiconductor layer in contact with the first gate electrode, the conductive layer, and side surfaces of a groove portion in the insulating layer;
a second gate insulating layer covering the oxide semiconductor layer; and
a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the groove portion is provided between the first gate electrode and the conductive layer.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein a top surface of the first gate electrode and a top surface of the conductive layer are aligned with a surface of the insulating layer.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the oxide semiconductor layer is in contact with a bottom surface of the groove portion.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein a depth of the groove portion is at least one-half of a distance between the first gate electrode and the conductive layer seen from the above.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein the conductive layer is formed from the same layer and of the same material as the first gate electrode.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, wherein the oxide semiconductor layer comprises a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.

### Claim 8

A semiconductor memory device comprising:
a semiconductor layer;
a first gate insulating layer over the semiconductor layer;
an insulating layer over the first gate insulating layer;
a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer;
a first conductive layer provided in the insulating layer;
an oxide semiconductor layer in contact with the first gate electrode, the first conductive layer, and side surfaces of a groove portion in the insulating layer;
a second gate insulating layer covering the oxide semiconductor layer;
a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween; and
a capacitor comprising a second conductive layer formed from the same layer and of the same material as the second gate electrode,
wherein the oxide semiconductor layer and the second gate insulating layer are interposed between the second conductive layer and the first gate electrode.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, wherein the groove portion is provided between the first gate electrode and the first conductive layer.

### Claim 10 (depends on 8)

The semiconductor memory device according to claim 8, wherein a top surface of the first gate electrode and a top surface of the first conductive layer are aligned with a surface of the insulating layer.

### Claim 11 (depends on 8)

The semiconductor memory device according to claim 8, wherein the oxide semiconductor layer is in contact with a bottom surface of the groove portion.

### Claim 12 (depends on 8)

The semiconductor memory device according to claim 8, wherein a depth of the groove portion is at least one-half of a distance between the first gate electrode and the first conductive layer seen from the above.

### Claim 13 (depends on 8)

The semiconductor memory device according to claim 8, wherein the first conductive layer is formed from the same layer and of the same material as the first gate electrode.

### Claim 14 (depends on 8)

The semiconductor memory device according to claim 8, wherein the oxide semiconductor layer comprises a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.

### Claim 15

A semiconductor memory device comprising:
a semiconductor layer;
a first gate insulating layer over the semiconductor layer;
an insulating layer over the first gate insulating layer;
a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer;
a conductive layer provided in the insulating layer;
an oxide semiconductor layer in contact with the first gate electrode, the conductive layer, side surfaces of a groove portion in the insulating layer, and the first gate insulating layer;
a second gate insulating layer covering the oxide semiconductor layer; and
a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween.

### Claim 16 (depends on 15)

The semiconductor memory device according to claim 15, wherein the groove portion is provided between the first gate electrode and the conductive layer.

### Claim 17 (depends on 15)

The semiconductor memory device according to claim 15, wherein a top surface of the first gate electrode and a top surface of the conductive layer are aligned with a surface of the insulating layer.

### Claim 18 (depends on 15)

The semiconductor memory device according to claim 15, wherein a depth of the groove portion is at least one-half of a distance between the first gate electrode and the conductive layer seen from the above.

### Claim 19 (depends on 15)

The semiconductor memory device according to claim 15, wherein the conductive layer is formed from the same layer and of the same material as the first gate electrode.

### Claim 20 (depends on 15)

The semiconductor memory device according to claim 15, wherein the oxide semiconductor layer comprises a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.