# US 8,772,848 B2 · Circuit structures, memory circuitry, and methods

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- Number: US 8,772,848 B2
- Document ID: US8772848B2
- Status: Granted
- Kind: B2
- Application number: 13/191,293
- Filed: 2011-07-26
- Published: 2013-01-31
- Granted: 2014-07-08
- Earliest claimed: 2011-07-26
- Assignees: Micron Technology, Inc.
- Applicants: John K. Zahurak; Sanh D. Tang; Lars P. Heineck; Martin C. Roberts; Wolfgang Mueller; Haitao Liu
- Inventors: John K. Zahurak; Sanh D. Tang; Lars P. Heineck; Martin C. Roberts; Wolfgang Mueller; Haitao Liu
- Web page: https://patentgrep.com/patent/US8772848B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/711: {having floating bodies}
- H10D 62/60: Impurity distributions or concentrations
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/01: Manufacture or treatment
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/881: {Switching materials}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10W 20/43: Layouts of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

## Claims

### Claim 1

A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material, amorphous material in the array and peripheral regions between the insulator material and the conductive material, the amorphous material in the array and peripheral regions being directly against the conductive material;
the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor material of the floating bodies;
conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region; and
the second semiconductor material in the peripheral region comprising a PMOS region, the PMOS region comprising first dopant concentration n-type material and second dopant concentration n-type material that are directly against one another, the second dopant concentration being higher than the first dopant concentration, the second dopant concentration n-type material being directly against the conductive material in the PMOS region and being laterally discontinuous across the floating body of the horizontal circuit devices in the PMOS region.

### Claim 2

A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material;
the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor material of the floating bodies;
conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region;
the second semiconductor material in the peripheral region comprising a PMOS region, the PMOS region comprising first dopant concentration n-type material and second dopant concentration n-type material that are directly against one another, the second dopant concentration being higher than the first dopant concentration, the second dopant concentration n-type material being directly against the conductive material in the PMOS region and being laterally discontinuous across the floating body of the horizontal circuit devices in the PMOS region; and
dielectric material over the conductive material in the PMOS region, the second dopant concentration n-type material being elevationally below and directly against the dielectric material elevationally between the dielectric material and the conductive material in the PMOS region.

### Claim 3

A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material, amorphous material in the array and peripheral regions between the insulator material and the conductive material, the amorphous material in the array and peripheral regions being directly against the conductive material; the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor material of the floating bodies;
conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region; and
the second semiconductor material in the peripheral region comprising an NMOS region, the NMOS region comprising first dopant concentration p-type material and second dopant concentration p-type material that are directly against one another, the second dopant concentration being higher than the first dopant concentration, the second dopant concentration p-type material being directly against the conductive material in the NMOS region and being laterally discontinuous across the floating body of the horizontal circuit devices in the NMOS region.

### Claim 4

A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material;
the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor material of the floating bodies;
conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region; and
the second semiconductor material in the peripheral region comprising an NMOS region, the NMOS region comprising first dopant concentration p-type material and second dopant concentration p-type material that are directly against one another, the second dopant concentration being higher than the first dopant concentration, the second dopant concentration p-type material being directly against the conductive material in the NMOS region and being laterally discontinuous across the floating body of the horizontal circuit devices in the NMOS region; and
dielectric material over the conductive material in the NMOS region, the second dopant concentration p-type material being elevationally below and directly against the dielectric material elevationally between the dielectric material and the conductive material in the NMOS region.

### Claim 5

A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material, amorphous material in the array and peripheral regions between the insulator material and the conductive material, the amorphous material in the array and peripheral regions being directly against the conductive material;
the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor material of the floating bodies;
conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region; and
the second semiconductor material in the peripheral region comprising an NMOS region having the horizontal circuit devices therein which comprise NMOS field effect transistors having source/drain regions, the NMOS region comprising p-type material and n-type material that are directly against one another and both of which are elevationally inward of the source/drain regions, the n-type material being directly against the conductive material in the NMOS region and being laterally discontinuous across the floating body of the NMOS field effect transistors.

### Claim 6

A circuit structure, comprising:
a substrate comprising an array region and a peripheral region; the substrate in the array and peripheral regions comprising insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material; the array region comprising vertical circuit devices comprising the second semiconductor material, the peripheral region comprising horizontal circuit devices comprising the second semiconductor material;
the horizontal circuit devices in the peripheral region individually comprising a floating body comprising the second semiconductor material, the conductive material in the peripheral region being under and electrically coupled to the second semiconductor material of the floating bodies;
conductive straps in the array region under the vertical circuit devices, the conductive straps comprising the conductive material and individually being electrically coupled to a plurality of the vertical circuit devices in the array region; and
the second semiconductor material in the peripheral region comprising an NMOS region having the horizontal circuit devices therein which comprise NMOS field effect transistors having source/drain regions, the NMOS region comprising p-type material and n-type material that are directly against one another and both of which are elevationally inward of the source/drain regions, the n-type material being directly against the conductive material in the NMOS region and being laterally discontinuous across the floating body of the NMOS field effect transistors; and
dielectric material over the conductive material in the NMOS region, the p-type material being elevationally below and directly against the dielectric material elevationally between the dielectric material and the conductive material in the NMOS region.

### Claim 7 (depends on 1)

The circuit structure of claim 1 wherein the second dopant concentration n-type material is longitudinally continuous between immediately longitudinally adjacent of the horizontal circuit devices in the PMOS region.

### Claim 8 (depends on 2)

The circuit structure of claim 2 wherein the second dopant concentration n-type material is longitudinally continuous between immediately longitudinally adjacent of the horizontal circuit devices in the PMOS region.

### Claim 9 (depends on 1)

The circuit structure of claim 1 comprising a conductive contact directly against the second dopant concentration n-type material in the PMOS region.

### Claim 10 (depends on 2)

The circuit structure of claim 2 comprising a conductive contact directly against the second dopant concentration n-type material in the PMOS region.

### Claim 11 (depends on 3)

The circuit structure of claim 3 comprising a conductive contact directly against the second dopant concentration p-type material in the NMOS region.

### Claim 12 (depends on 4)

The circuit structure of claim 4 comprising a conductive contact directly against the second dopant concentration p-type material in the NMOS region.

### Claim 13 (depends on 5)

The circuit structure of claim 5 comprising a conductive contact directly against the second dopant concentration p-type material in the NMOS region.

### Claim 14 (depends on 6)

The circuit structure of claim 6 comprising a conductive contact directly against the second dopant concentration p-type material in the NMOS region.