# US 8,772,839 B2 · Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer

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- Number: US 8,772,839 B2
- Document ID: US8772839B2
- Status: Granted
- Kind: B2
- Application number: 12/753,793
- Filed: 2010-04-02
- Published: 2010-07-29
- Granted: 2014-07-08
- Earliest claimed: 2008-03-13
- Assignees: Tela Innovations, Inc.
- Applicants: Scott T. Becker; Jim Mali; Carole Lambert
- Inventors: Scott T. Becker; Jim Mali; Carole Lambert
- Web page: https://patentgrep.com/patent/US8772839B2

## CPC

- H10D 84/907: {CMOS gate arrays}
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/10: SRAM devices comprising bipolar components
- H10B 10/12: {comprising a MOSFET load element}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 89/10: Integrated device layouts
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H10D 84/953: {Sub-micron technology}
- H10D 84/975: {Wiring regions or routing}
- H10D 84/987: {Three levels of metal}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. A gate electrode level region is formed in accordance with a virtual grate defined by virtual lines that extend in only a first parallel direction, such that an equal perpendicular spacing exists between adjacent ones of the virtual lines. Each of a number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned with a virtual line of the virtual grate. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected, and the gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected.

## Claims

### Claim 1

An integrated circuit, comprising:
a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein each of the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated from the third gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and
wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction;
a first gate contact defined to physically contact the first gate level feature;
a second gate contact defined to physically contact the second gate level feature;
a third gate contact defined to physically contact the third gate level feature;
a fourth gate contact defined to physically contact the fourth gate level feature;
a fifth gate contact defined to physically contact the fifth gate level feature;
a sixth gate contact defined to physically contact the sixth gate level feature,
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the second, third, fourth, and fifth gate contacts is located over the inner portion of the gate electrode level region,
wherein the third gate contact is offset in the first direction from the fourth gate contact; and
a plurality of interconnect level regions formed above the gate electrode level region; and
a first electrical connection defined to electrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region is linear-shaped.

### Claim 2 (depends on 1)

An integrated circuit as recited in claim 1, wherein the gate electrodes of the first, second, third, and fourth transistors of the first transistor type are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the first transistor type is substantially equal to an integer multiple of the gate pitch, and
wherein the gate electrodes of the first, second, third, and fourth transistors of the second transistor type are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the second transistor type is substantially equal to an integer multiple of the gate pitch.

### Claim 3 (depends on 2)

An integrated circuit as recited in claim 2, wherein the gate electrode level region includes a seventh gate level feature that forms a gate electrode of a fifth transistor of the first transistor type and a gate electrode of a fifth transistor of the second transistor type.

### Claim 4 (depends on 3)

An integrated circuit as recited in claim 3, wherein all gate level features within the gate electrode level region are linear shaped and extend lengthwise in the first direction.

### Claim 5 (depends on 4)

An integrated circuit as recited in claim 4, wherein the gate electrode level region includes an eighth gate level feature that does not form a gate electrode of a transistor, the eighth gate level feature positioned such that a distance as measured in the second direction between a first-direction-oriented centerline of the eighth gate level feature and a first-direction-oriented centerline of a gate electrode of a transistor within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.

### Claim 6 (depends on 1)

An integrated circuit as recited in claim 1, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of the first transistor type,
wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type,
wherein the fourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type,
wherein the fifth gate level feature has an extension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type, and
wherein at least two of the extension distances of the second, third, fourth, and fifth gate level features are different.

### Claim 7 (depends on 6)

An integrated circuit as recited in claim 6, wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction.

### Claim 8 (depends on 7)

An integrated circuit as recited in claim 7, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.

### Claim 9 (depends on 8)

An integrated circuit as recited in claim 8, wherein each gate level feature within the gate electrode level region is linear-shaped.

### Claim 10 (depends on 9)

An integrated circuit as recited in claim 9, wherein the gate electrodes of the first and second transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the second and third transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the third and fourth transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the first and second transistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the second and third transistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the third and fourth transistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines.

### Claim 11 (depends on 9)

An integrated circuit as recited in claim 9, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level region through which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the second electrical connection within the one interconnect level region is linear-shaped.

### Claim 12 (depends on 1)

An integrated circuit as recited in claim 1, wherein each gate level feature within the gate electrode level region is linear-shaped.

### Claim 13 (depends on 12)

An integrated circuit as recited in claim 12, wherein the gate electrodes of the first and second transistors of the first transistor type are separated by a gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the second and third transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the third and fourth transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the first and second transistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the second and third transistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and
wherein the gate electrodes of the third and fourth transistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines.

### Claim 14 (depends on 13)

An integrated circuit as recited in claim 13, wherein all gate level features within the gate electrode level region are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of two adjacently placed gate level features within the gate electrode level region is substantially equal to the gate pitch.

### Claim 15 (depends on 14)

An integrated circuit as recited in claim 14, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of the first transistor type,
wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type,
wherein the fourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type,
wherein the fifth gate level feature has an extension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type, and
wherein at least two of the extension distances of the second, third, fourth, and fifth gate level features are different.

### Claim 16 (depends on 12)

An integrated circuit as recited in claim 12, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level region through which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the second electrical connection within the one interconnect level region is linear-shaped.

### Claim 17 (depends on 16)

An integrated circuit as recited in claim 16, wherein all gate level features within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of two adjacently placed gate level features within the gate electrode level region is substantially equal to the gate pitch.

### Claim 18 (depends on 1)

An integrated circuit as recited in claim 1, wherein a length of the second gate level feature as measured in the first direction is different than a length of the fourth gate level feature as measured in the first direction.

### Claim 19 (depends on 18)

An integrated circuit as recited in claim 18, wherein a length of the third gate level feature as measured in the first direction is different than a length of the fifth gate level feature as measured in the first direction.

### Claim 20 (depends on 19)

An integrated circuit as recited in claim 19, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.

### Claim 21 (depends on 20)

An integrated circuit as recited in claim 20, wherein each gate level feature within the gate electrode level region is linear-shaped.

### Claim 22 (depends on 21)

An integrated circuit as recited in claim 21, wherein the gate electrode level region includes a seventh gate level feature that does not form a gate electrode of a transistor.

### Claim 23 (depends on 22)

An integrated circuit as recited in claim 22, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type,
wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, and
wherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type.

### Claim 24 (depends on 23)

An integrated circuit as recited in claim 23, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level region through which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the second electrical connection within the one interconnect level region is linear-shaped.

### Claim 25

A method for creating a layout of an integrated circuit, comprising:
operating a computer to define a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein each of the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated from the third gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and
wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction;
operating a computer to define a first gate contact defined to physically contact the first gate level feature;
operating a computer to define a second gate contact defined to physically contact the second gate level feature;
operating a computer to define a third gate contact defined to physically contact the third gate level feature;
operating a computer to define a fourth gate contact defined to physically contact the fourth gate level feature;
operating a computer to define a fifth gate contact defined to physically contact the fifth gate level feature;
operating a computer to define a sixth gate contact defined to physically contact the sixth gate level feature,
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the second, third, fourth, and fifth gate contacts is located over the inner portion of the gate electrode level region,
wherein the third gate contact is offset in the first direction from the fourth gate contact; and
operating a computer to define a plurality of interconnect level regions formed above the gate electrode level region; and
operating a computer to define a first electrical connection to electrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region is linear-shaped.

### Claim 26

A computer readable medium having program instructions stored thereon for generating a layout of an integrated circuit, comprising:
program instructions for defining a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein each of the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated from the third gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and
wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction;
program instructions for defining a first gate contact defined to physically contact the first gate level feature;
program instructions for defining a second gate contact defined to physically contact the second gate level feature;
program instructions for defining a third gate contact defined to physically contact the third gate level feature;
program instructions for defining a fourth gate contact defined to physically contact the fourth gate level feature;
program instructions for defining a fifth gate contact defined to physically contact the fifth gate level feature;
program instructions for defining a sixth gate contact defined to physically contact the sixth gate level feature,
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the second, third, fourth, and fifth gate contacts is located over the inner portion of the gate electrode level region,
wherein the third gate contact is offset in the first direction from the fourth gate contact; and
program instructions for defining a plurality of interconnect level regions formed above the gate electrode level region; and
program instructions for defining a first electrical connection to electrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region is linear-shaped.