# US 8,772,837 B2 · Semiconductor device comprising a lateral bipolar transistor

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- Number: US 8,772,837 B2
- Document ID: US8772837B2
- Status: Granted
- Kind: B2
- Application number: 14/032,515
- Filed: 2013-09-20
- Published: 2014-02-06
- Granted: 2014-07-08
- Earliest claimed: 2007-12-20
- Assignees: Asahi Kasei Microdevices Corporation
- Applicants: Asahi Kasei Microdevices Corporation
- Inventors: Tomislav Suligoj; Marko Koricic; Hidenori Mochizuki; Soichi Morita
- Web page: https://patentgrep.com/patent/US8772837B2

## CPC

- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/60: Lateral BJTs
- H10D 62/134: {of lateral BJTs}
- H10D 62/184: {of lateral BJTs}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11. An emitter electrode 31A and a collector electrode 31B are formed in the open region 21 and are composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched.

## Claims

### Claim 1

A semiconductor device comprising a lateral bipolar transistor,
the lateral bipolar transistor including:
a substrate including a first conductive layer;
an active region located on the first conductive layer and having such a shape as to protrude from the first conductive layer and have an upper surface and at least one side surface in contact with the upper surface; and
a device isolating oxide film partially covering the side surface of the active region,
wherein the active region includes a second conductive layer having a polarity different from that of the first conductive layer, and
wherein the active region includes a third conductive layer having the same polarity as that of the first conductive layer at two opposing positions of the upper surface and said at least one side surface,
wherein the third conductive layer includes a fourth conductive layer having the same polarity as that of the second conductive layer,
wherein the fourth conductive layer is connected to an emitter electrode,
further comprising at least two collector contact electrodes, wherein the active region is electrically connected to said at least two collector contact electrodes, and said at least two collector contact electrodes are arranged in such a manner that a line connecting said at least two collector contact electrodes is substantially orthogonal to another line connecting said two opposing positions of said at least one side surface.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein an impurity concentration and a width of the active region are set so that the entire of the active region becomes depleted when the lateral bipolar transistor is electrically enabled.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein a ratio between the impurity concentration of the active region and an impurity concentration of the third conductive layer is within a range from 1:10 to 1:10000.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising a CMOS transistor integrated on the substrate.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, further comprising a CMOS transistor integrated on the substrate.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising a CMOS transistor integrated on the substrate.