# US 8,772,834 B2 · High electron mobility transistor and method of driving the same

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- Number: US 8,772,834 B2
- Document ID: US8772834B2
- Status: Granted
- Kind: B2
- Application number: 13/868,579
- Filed: 2013-04-23
- Published: 2014-04-17
- Granted: 2014-07-08
- Earliest claimed: 2012-10-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Woo-chul Jeon; Jong-seob Kim; Ki-yeol Park; Young-hwan Park; Jae-joon Oh; Jong-bong Ha; Jai-kwang Shin
- Web page: https://patentgrep.com/patent/US8772834B2

## CPC

- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/473: {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/411: {for FETs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.

## Claims

### Claim 1

A high electron mobility transistor (HEMT) comprising:
a channel layer including a first semiconductor material;
a channel supply layer on the channel layer,
the channel supply layer including a second semiconductor material,
the channel supply layer configured to induce a two-dimensional electron gas (2DEG) in the channel layer;
a source electrode and a drain electrode at both sides of the channel supply layer;
a depletion-forming layer on the channel supply layer,
the depletion-forming layer configured to form a depletion region in the 2DEG;
a first gate electrode on the depletion-forming layer,
the first gate electrode between the source electrode and the drain electrode; and
at least one second gate electrode separated from the first gate electrode on the depletion-forming layer and between the source electrode and the drain electrode.

### Claim 2 (depends on 1)

The HEMT of claim 1, wherein
the HEMT includes one second gate electrode,
the second gate electrode is a floating electrode, and
the first and second gate electrodes are configured such that applying a first gate voltage to the first gate electrode induces a second gate voltage in the second gate electrode.

### Claim 3 (depends on 2)

The HEMT of claim 2, wherein
the first gate electrode and the second gate electrode are connected to each other by the depletion-forming layer, and
the first gate electrode is configured to induce the second gate voltage in the second gate electrode via the depletion-forming layer if the first gate voltage is applied to the first gate electrode.

### Claim 4 (depends on 3)

The HEMT of claim 3, wherein the depletion-forming layer is a strip shape between the first gate electrode and the second gate electrode.

### Claim 5 (depends on 3)

The HEMT of claim 3, wherein the second gate electrode and the source electrode are connected to each other by the depletion-forming layer.

### Claim 6 (depends on 5)

The HEMT of claim 5, wherein the depletion-forming layer is a strip shape between the source electrode and the second gate electrode.

### Claim 7 (depends on 2)

The HEMT of claim 2, further comprising:
a coating layer on at least a portion of an upper surface of the channel supply layer.

### Claim 8 (depends on 7)

The HEMT of claim 7, wherein a material of the coating layer is the same as a material of the depletion-forming layer.

### Claim 9 (depends on 8)

The HEMT of claim 8, wherein a thickness of the coating layer is less than a thickness of the depletion-forming layer.

### Claim 10 (depends on 2)

The HEMT of claim 2, wherein the first gate electrode is configured to induce the second gate voltage in the second gate electrode via an upper surface of the channel supply layer.

### Claim 11 (depends on 2)

The HEMT of claim 2, wherein the second gate voltage induced in the second gate electrode is determined by the first gate voltage applied to the first gate electrode, a gap between the first gate electrode and the second gate electrode, and a gap between the second gate electrode and the source electrode.

### Claim 12 (depends on 11)

The HEMT of claim 11, wherein a threshold voltage of the HEMT is determined based on the second gate voltage induced in the second gate electrode.

### Claim 13 (depends on 1)

The HEMT of claim 1, wherein the first semiconductor material is a gallium nitride (GaN) group material.

### Claim 14 (depends on 1)

The HEMT of claim 1, wherein the second semiconductor material includes at least one nitride that includes at least one of aluminum (Al), gallium (Ga), indium (In) and boron (B).

### Claim 15 (depends on 1)

The HEMT of claim 1, wherein the depletion-forming layer includes a p-type semiconductor material.

### Claim 16 (depends on 15)

The HEMT of claim 15, wherein the depletion-forming layer includes a group III-V nitride semiconductor material.

### Claim 17 (depends on 1)

A method of driving the HEMT of claim 1, comprising:
applying a first gate voltage to the first gate electrode,
inducing a second gate voltage in a floating electrode by applying the first gate voltage to the first gate electrode,
wherein the HEMT includes one second gate electrode and the second gate electrode is the floating electrode.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first gate electrode and the second gate electrode are connected to each other by the depletion-forming layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second gate electrode and the source electrode are connected to each other by the depletion-forming layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the HEMT further includes a coating layer on at least a portion of an upper surface of the channel supply layer.

### Claim 21 (depends on 17)

The method of claim 17, wherein applying the first gate voltage to the first gate electrode induces the second gate voltage in the second gate electrode via an upper surface of the channel supply layer.

### Claim 22 (depends on 17)

The method of claim 17, wherein a threshold voltage of the HEMT is determined by the second gate voltage induced in the second gate electrode.

### Claim 23 (depends on 17)

The method of claim 17, wherein the second gate voltage induced in the second gate electrode is determined by the first gate voltage applied to the first gate electrode, a gap between the first gate electrode and the second gate electrode, and a gap between the second gate electrode and the source electrode.

### Claim 24 (depends on 1)

The HEMT of claim 1, wherein the at least one second gate electrode is one second gate electrode between the first gate electrode and the source electrode.

### Claim 25

A high electron mobility transistor (HEMT) comprising:
a channel layer;
a channel supply layer on the channel layer,
the channel supply layer configured to induce a two-dimensional electron gas (2DEG) in the channel layer;
a source electrode and a drain electrode spaced apart on the channel layer;
a depletion-forming layer on the channel supply layer,
the depletion-forming layer configured to form a depletion region in the 2DEG; and
a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode,
the plurality of gate electrodes including a first gate electrode and a second gate electrode laterally spaced apart from each other.

### Claim 26 (depends on 25)

The HEMT of claim 25, wherein
the second gate electrode is a floating electrode between the source electrode and the first gate electrode, and
the first and second gate electrodes are configured such that applying a first gate voltage to the first gate electrode induces a second gate voltage in the second gate electrode.

### Claim 27 (depends on 26)

The HEMT of claim 26, wherein
the plurality of electrodes includes a third gate electrode on the depletion-forming layer, and
the third gate electrode is spaced apart between the second gate electrode and the source electrode.

### Claim 28 (depends on 27)

The HEMT of claim 27, wherein a portion of the depletion-forming layer extends between at least two of the first electrode, the second electrode, the third electrode, and the source electrode.

### Claim 29 (depends on 26)

The HEMT of claim 26, wherein a portion of the depletion-forming layer extends from the second gate electrode to at least one of the source electrode and the first gate electrode.

### Claim 30 (depends on 26)

The HEMT of claim 26, wherein the depletion forming layer exposes at least one of:
an entire upper surface of the channel supply layer between the source electrode and the second gate electrode,
an entire upper surface of the channel supply layer between the second gate electrode and the first gate electrode.

### Claim 31 (depends on 26)

The HEMT of claim 26, wherein at least one of the source electrode and the drain electrode is connected to a sidewall of the channel supply layer.

### Claim 32 (depends on 26)

The HEMT of claim 26, wherein the depletion forming layer has a grid shape.

### Claim 33 (depends on 25)

The HEMT of claim 25, wherein channel layer includes a group III-V compound semiconductor.

### Claim 34 (depends on 25)

The HEMT of claim 25, wherein a material of the channel supply layer is different than a material of the channel layer in terms of at least one of a polarization characteristic, an energy band gap, and a lattice constant.

### Claim 35 (depends on 25)

The HEMT of claim 25, wherein the depletion-forming layer includes a p-type semiconductor material.

### Claim 36 (depends on 25)

The HEMT of claim 25, wherein the second gate electrode is configured to raise a threshold voltage of the HEMT compared to a similar-formed HEMT that does not include the second gate electrode.

### Claim 37 (depends on 25)

A method of driving the HEMT of claim 25, comprising:
applying a first gate voltage to the first gate electrode; and
inducing a second gate voltage in the second gate electrode by applying the first gate voltage to the first gate electrode.

### Claim 38 (depends on 37)

The method of claim 37, wherein
the applying the first gate voltage includes forming a first channel under the first gate electrode in the channel layer, and
the first gate voltage is greater than a first threshold voltage for forming the first channel.

### Claim 39 (depends on 38)

The method of claim 38, wherein
the applying the first gate voltage induces the second gate voltage in the second gate electrode at a level that is greater than a second threshold voltage for forming a second channel under the second gate electrode in the channel layer, and
the applying the first gate voltage further includes forming the second channel under the second gate electrode in the channel layer.