# US 8,772,833 B2 · Power semiconductor device and fabrication method thereof

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- Number: US 8,772,833 B2
- Document ID: US8772833B2
- Status: Granted
- Kind: B2
- Application number: 13/592,560
- Filed: 2012-08-23
- Published: 2013-03-21
- Granted: 2014-07-08
- Earliest claimed: 2011-09-21
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Woo Jin Chang; Jong Won Lim; Ho Kyun Ahn; Sang Choon Ko; Sung Bum Bae; Chull Won Ju; Young Rak Park; Jae Kyoung Mun; Eun Soo Nam
- Inventors: Woo Jin Chang; Jong Won Lim; Ho Kyun Ahn; Sang Choon Ko; Sung Bum Bae; Chull Won Ju; Young Rak Park; Jae Kyoung Mun; Eun Soo Nam
- Web page: https://patentgrep.com/patent/US8772833B2

## CPC

- H10D 30/0512: {of FETs having PN homojunction gates}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/01: Manufacture or treatment
- H10D 64/111: {Field plates}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

## Claims

### Claim 1

A power semiconductor device, comprising:
a source electrode and a drain electrode formed on a substrate;
a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate;
a gate electrode formed on the etched part;
a field plate formed on the dielectric layer between the gate electrode and the drain electrode, wherein the dielectric layer includes an upper surface in direct contact with both of the gate electrode and the field plate; and
a metal configured to connect the field plate and the source electrode.

### Claim 2 (depends on 1)

The power semiconductor device of claim 1, wherein the metal is formed on an equal plane on which the field plate is formed.

### Claim 3 (depends on 2)

The power semiconductor device of claim 2, wherein the metal is formed in a curve shape.

### Claim 4 (depends on 1)

The power semiconductor device of claim 1, wherein the gate electrode is a gamma (Γ) shaped gate electrode or a T shaped gate electrode.

### Claim 5 (depends on 1)

The power semiconductor device of claim 1, wherein corner parts of the source electrode, the drain electrode, the gate electrode and the field plate are formed in a curve shape.

### Claim 6 (depends on 1)

The power semiconductor device of claim 1, further comprising a further field plate formed below the field plate through a fine etching process of the dielectric layer.

### Claim 7

A power semiconductor device, comprising:
a source electrode and a drain electrode formed on a substrate;
a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate;
a gate electrode formed on the etched part;
a first field plate formed on the dielectric layer between the gate electrode and the drain electrode, wherein the dielectric layer includes an upper surface in direct contact with both of the gate electrode and the first field plate;
a second field plate spaced from the gate electrode and formed over an area from the source electrode to the first field plate; and
a metal configured to connect the source electrode and the second field plate, and the first field plate and the second field plate, respectively.

### Claim 8 (depends on 7)

The power semiconductor device of claim 7, wherein the gate electrode is a gamma (Γ) shaped gate electrode or a T shaped gate electrode.

### Claim 9 (depends on 7)

The power semiconductor device of claim 7, wherein corner parts of the source electrode, the drain electrode, the gate electrode, the first field plate and the second field plate are formed in a curve shape.

### Claim 10 (depends on 7)

The power semiconductor device of claim 7, further comprising a further field plate formed on a lower part of the first field plate through a fine etching process of the dielectric layer.