# US 8,772,831 B2 · III-nitride growth method on silicon substrate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,831 B2
- Document ID: US8772831B2
- Status: Granted
- Kind: B2
- Application number: 13/290,534
- Filed: 2011-11-07
- Published: 2013-05-09
- Granted: 2014-07-08
- Earliest claimed: 2011-11-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Chi-Ming Chen; Po-Chun Liu; Hung-Ta Lin; Chin-Cheng Chang; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang
- Inventors: Chi-Ming Chen; Po-Chun Liu; Hung-Ta Lin; Chin-Cheng Chang; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang
- Web page: https://patentgrep.com/patent/US8772831B2

## CPC

- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- C30B 25/183: {being provided with a buffer layer, e.g. a lattice matching layer}
- C30B 29/403: {AIII-nitrides}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3216: {Nitrides}
- H10P 14/3254: {Graded layers}
- H10P 14/3416: {Nitrides}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.

## Claims

### Claim 1

A circuit structure comprising:
a silicon substrate;
a patterned dielectric layer over and in direct contact with a top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through the dielectric layer;
a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;
a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer; and
a graded group III-V superlattice layer over the lateral growth layer.

### Claim 2

A circuit structure comprising:
a silicon substrate;
a patterned dielectric layer over and in direct contact with a top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through the dielectric layer, said plurality of vias arranged in a hexagonal pattern;
a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;
a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer;
a graded group III-V superlattice layer over the lateral growth layer; and
a bulk layer of group III-V compound semiconductor layer over the lateral growth layer.

### Claim 3 (depends on 2)

The circuit structure of claim 2, wherein the patterned dielectric layer is a thermal silicon oxide layer.

### Claim 4 (depends on 2)

The circuit structure of claim 2, wherein the vertical growth layer and the lateral growth layer consist essentially of a same material.

### Claim 5 (depends on 2)

The circuit structure of claim 2, wherein the vias have an aspect ratio of about 2 to about 5.

### Claim 6 (depends on 5)

The circuit structure of claim 5, wherein each via is separated from an adjacent via by about 2 microns to about 5 microns.

### Claim 7 (depends on 5)

The circuit structure of claim 5, wherein each via is about 3000 angstroms to about 5000 angstroms deep.

### Claim 8 (depends on 5)

The circuit structure of claim 5, wherein each via has a diameter of about 1000 angstroms to about 2000 angstroms.

### Claim 9 (depends on 5)

The circuit structure of claim 5, wherein a size and spacing of the plurality of vias varies across the patterned dielectric layer.

### Claim 10 (depends on 2)

The circuit structure of claim 2, wherein the bulk layer is about 0.5 to about 3 microns thick.

### Claim 11 (depends on 2)

The circuit structure of claim 2, wherein the circuit structure is a light emitting diode.

### Claim 12 (depends on 2)

The circuit structure of claim 2, wherein the circuit structure is a high electron mobility transistor.

### Claim 13

A high electron mobility transistor comprising:
a silicon substrate;
a patterned dielectric layer over and directly contacting a top surface of the silicon substrate, the patterned dielectric layer comprising a plurality of vias through the dielectric layer, said plurality of vias each having hexagonal openings;
a vertical growth layer disposed over the substrate and within the vias in the patterned dielectric layer;
a lateral growth layer of group-III to group-V (III-V) compound semiconductor layer disposed over the vertical growth layer and the patterned dielectric layer, forming a continuous layer over the patterned dielectric layer and the vertical growth layer;
a graded group III-V superlattice layer over the lateral growth layer; and
a bulk layer of group III-V compound semiconductor layer over the lateral growth layer.

### Claim 14 (depends on 13)

The high electron mobility transistor of claim 13, wherein the silicon substrate has a crystal orientation of [111].

### Claim 15 (depends on 13)

The high electron mobility transistor of claim 13, wherein the patterned dielectric layer is a thermal silicon oxide layer.

### Claim 16 (depends on 13)

The high electron mobility transistor of claim 13, wherein the vertical growth layer and the lateral growth layer consist essentially of a same material.

### Claim 17 (depends on 13)

The high electron mobility transistor of claim 13, wherein the vias have an aspect ratio of about 2 to about 5.

### Claim 18 (depends on 17)

The high electron mobility transistor of claim 17, wherein each via is separated from an adjacent via by about 2 microns to about 5 microns.

### Claim 19 (depends on 17)

The high electron mobility transistor of claim 17, wherein each via is about 3000 angstroms to about 5000 angstroms deep.

### Claim 20 (depends on 17)

The high electron mobility transistor of claim 17, wherein each via has a diameter of about 1000 angstroms to about 2000 angstroms.

### Claim 21 (depends on 13)

The high electron mobility transistor of claim 13, wherein each via has slanted sidewalls.

### Claim 22 (depends on 13)

The high electron mobility transistor of claim 13, wherein the bulk layer is about 05 to about 3 microns thick.