# US 8,772,830 B2 · Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,830 B2 - Document ID: US8772830B2 - Status: Granted - Kind: B2 - Application number: 12/811,074 - Filed: 2008-12-26 - Published: 2011-01-27 - Granted: 2014-07-08 - Earliest claimed: 2007-12-28 - Assignees: Sumitomo Chemical Company, Limited - Applicants: Tomoyuki Takada; Sadanori Yamanaka; Masahiko Hata - Inventors: Tomoyuki Takada; Sadanori Yamanaka; Masahiko Hata - Web page: https://patentgrep.com/patent/US8772830B2 ## CPC - H10D 62/405: {Orientations of crystalline planes} - H10D 10/021: {of heterojunction BJTs [HBT]} - H10D 10/821: {Vertical heterojunction BJTs} - H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions - H10P 14/271: {characterised by the preparation of substrate for selective deposition} - H10P 14/2905: {Silicon, silicon germanium or germanium} - H10P 14/2926: {Crystal orientations} - H10P 14/3211: {Silicon, silicon germanium or germanium} - H10P 14/3221: {Arsenides} - H10P 14/3258: {Crystal orientation} - H10P 14/3421: {Arsenides} - H10P 14/24: using chemical vapour deposition [CVD] - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects. ## Claims ### Claim 1 A semiconductor wafer comprising: an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is epitaxially crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is epitaxially crystal-grown on the buffer layer, wherein the functional layer is an element formation layer that is a group 3-5 compound layer or a group 2-6 compound layer that lattice matches or pseudo-lattice matches with Ge, and the element formation layer has an arithmetic mean roughness value of no greater than 0.02 μm. ### Claim 2 (depends on 1) The semiconductor wafer according to claim 1, wherein the Ge layer is then annealed with a temperature and duration that enables movement of crystal defects. ### Claim 3 (depends on 2) The semiconductor wafer according to claim 2, wherein the annealing is repeated a plurality of times. ### Claim 4 (depends on 1) The semiconductor wafer according to claim 1, wherein the element formation layer is a group 3-5 compound layer that lattice matches or pseudo-lattice matches with Ge, in which a group 3 element includes at least one of Al, Ga, and In and a group 5 element includes at least one of N, P, As, and Sb. ### Claim 5 (depends on 1) The semiconductor wafer according to claim 1, wherein the inhibiting layer is an electric insulator. ### Claim 6 (depends on 5) The semiconductor wafer according to claim 5, wherein the inhibiting layer is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, or a combination of these layers. ### Claim 7 (depends on 1) The semiconductor wafer according to claim 1, wherein area of the open region is no greater than 1 mm2. ### Claim 8 (depends on 1) The semiconductor wafer according to claim 1, wherein the buffer layer is an InGaP layer. ### Claim 9 An electronic device comprising: an Si water; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is epitaxially crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; a functional layer that is epitaxially crystal-grown on the buffer layer; and an electronic element that is formed on the functional layer, wherein the functional layer is an element formation layer that is a group 3-5 compound layer or a group 2-6 compound layer that lattice matches or pseudo-lattice matches with Ge, and the element formation layer has an arithmetic mean roughness value of no greater than 0.02 μm. ### Claim 10 (depends on 9) The electronic device according to claim 9, wherein one electronic element is formed in each open region. ### Claim 11 (depends on 9) The electronic device according to claim 9, wherein wiring connected to the electronic element or a bonding pad for the wiring is formed on the covering region. ### Claim 12 (depends on 9) The electronic device according to claim 9, wherein a plurality of the covering regions and a plurality of the open regions are formed on the wafer, and the plurality of covering regions and the plurality of open regions are formed at uniform intervals. ### Claim 13 (depends on 9) The electronic device according to claim 9, wherein the electronic element is a heterojunction bipolar transistor. ### Claim 14 (depends on 9) The electronic device according to claim 9, comprising a plurality of the electronic elements, wherein the electronic elements are connected to each other. ### Claim 15 (depends on 9) The electronic device according to claim 9, comprising a plurality of the electronic elements, wherein the electronic elements are connected in parallel. ### Claim 16 (depends on 9) The electronic device according to claim 9, wherein the buffer layer is an InGaP layer. ### Claim 17 (depends on 9) The electronic device according to claim 9, wherein the element formation layer is a group 3-5 compound layer that lattice matches or pseudo-lattice matches with Ge, in which a group 3 element includes at least one of Al, Ga, and In and a group 5 element includes at least one of N, P, As, and Sb.