# US 8,772,827 B2 · Semiconductor device and manufacturing method

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- Number: US 8,772,827 B2
- Document ID: US8772827B2
- Status: Granted
- Kind: B2
- Application number: 13/491,581
- Filed: 2012-06-07
- Published: 2012-12-27
- Granted: 2014-07-08
- Earliest claimed: 2011-06-08
- Assignees: Rohm Co., Ltd.
- Applicants: Kenichi Yoshimochi
- Inventors: Kenichi Yoshimochi
- Web page: https://patentgrep.com/patent/US8772827B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 8/022: {of Zener diodes}
- H10D 8/25: Zener diodes
- H10D 12/032: {of vertical IGBTs}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D 84/617: {Combinations of vertical BJTs and only diodes}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/996: {using combined field effect technology and bipolar technology}
- H10D 89/10: Integrated device layouts
- H10W 10/0121: {in regions recessed from the surface, e.g. in trenches or grooves}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/50: Bond wires
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

## Claims

### Claim 1

A semiconductor device, comprising:
a first-conductivity-type semiconductor layer including an active region in which a transistor having a plurality of impurity regions is formed, and a marginal region surrounding an outer periphery of the active region;
a second-conductivity-type channel layer formed between the active region and the marginal region so as to form a front surface of the semiconductor layer;
at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer;
a gate insulation film formed on an inner surface of the at least one gate trench;
a gate electrode formed inside the gate insulation film in the at least one gate trench;
at least one isolation trench arranged between the active region and the marginal region to surround the outer periphery of the active region, and formed to extend from the front surface of the semiconductor layer through the channel layer, the at least one isolation trench having a depth equal to a depth of the at least one gate trench;
an inter-layer insulation film formed on the semiconductor layer;
a first terminal formed on the inter-layer insulation film and connected to the gate electrode through the inter-layer insulation film;
a bonding wire; and
a second terminal formed on the inter-layer insulation film and connected to one of the impurity regions of the transistor through the inter-layer insulation film, wherein
the at least one isolation trench is positioned directly below the second terminal, and
the second terminal is formed to cover the active region, and
the first terminal includes a gate pad to which the bonding wire is connected, and when seen in a plan view,
the gate pad surrounds an outer periphery of the second terminal, and
the at least one isolation trench bypasses the gate pad.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a trench insulation film formed on an inner surface of the at least one isolation trench; and
a buried electrode formed inside the trench insulation film in the at least one isolation trench.

### Claim 3 (depends on 1)

The device of claim 1, further comprising:
a first-conductivity-type high-concentration impurity region formed on a bottom surface of the at least one isolation trench,
wherein an impurity concentration of the high-concentration impurity region is higher than an impurity concentration of the semiconductor layer.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
a trench insulation film formed on an inner surface of the at least one isolation trench arranged directly below the second terminal; and
a buried electrode formed inside the trench insulation film in the at least one isolation trench,
wherein the second terminal is connected through the inter-layer insulation film to the buried electrode.

### Claim 5 (depends on 1)

The device of claim 1, wherein the at least one isolation trench includes a plurality of isolation trenches differing in perimeter from one another.

### Claim 6 (depends on 5)

The device of claim 5, further comprising buried electrodes formed in the plurality of isolation trenches,
wherein the second terminal is connected to a buried electrode of the buried electrodes disposed closest to the active region.

### Claim 7 (depends on 6)

The device of claim 6, wherein a width of the buried electrode connected to the second terminal is larger than widths of remaining buried electrodes of the buried electrodes, the remaining buried electrodes not being connected to the second terminal.

### Claim 8 (depends on 5)

The device of claim 5, wherein widths of the isolation trenches are uniform.

### Claim 9 (depends on 5)

The device of claim 5, wherein a pitch of the isolation trenches decreases in a direction extending from the active region toward the marginal region.

### Claim 10 (depends on 5)

The device of claim 5, wherein a pitch of the isolation trenches increases in a direction extending from the active region toward the marginal region.

### Claim 11 (depends on 5)

The device of claim 5, wherein a pitch of the isolation trenches is uniform.

### Claim 12 (depends on 5)

The device of claim 5, wherein the at least one gate trench includes a plurality of gate trenches, and a pitch of the isolation trenches is smaller than a pitch of the gate trenches.

### Claim 13 (depends on 5)

The device of claim 5, wherein a pitch of the isolation trenches is from 0.3 μm to 5.0 μm.

### Claim 14 (depends on 1)

The device of claim 1, wherein the at least one isolation trench is only one isolation trench.

### Claim 15 (depends on 1)

The device of claim 1,
wherein the at least one isolation trench is positioned directly below the first terminal.

### Claim 16 (depends on 1)

The device of claim 1, further comprising:
a first-conductivity-type high-concentration impurity region formed on a bottom surface of the at least one gate trench,
wherein an impurity concentration of the high-concentration impurity region is greater than an impurity concentration of the semiconductor layer.

### Claim 17 (depends on 1)

The device of claim 1, wherein the at least one isolation trench is recessed toward the active region with respect to the gate pad when seen in the plan view such that the at least one isolation trench inwardly bypasses the gate pad.

### Claim 18 (depends on 1)

The device of claim 1, wherein the at least one isolation trench protrudes away from the active region with respect to the gate pad when seen in the plan view such that the at least one isolation trench outwardly bypasses the gate pad.

### Claim 19 (depends on 1)

The device of claim 1, wherein the impurity regions include a MOS structure forming a trench-gate-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that includes the gate electrode, and wherein the MOS structure includes:
a first-conductivity-type source region exposed from the front surface of the semiconductor layer and configured to form a portion of a side surface of the at least one gate trench;
a second-conductivity-type channel region formed farther towards a rear surface of the semiconductor layer than the source region so as to make contact with the source region and configured to form a portion of the side surface of the at least one gate trench; and
a first-conductivity-type drain region formed farther towards the rear surface of the semiconductor layer than the channel region so as to make contact with the channel region and configured to form a bottom surface of the at least one gate trench.

### Claim 20 (depends on 1)

The device of claim 1, wherein the impurity regions include a MOS structure forming a trench-gate-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that includes the gate electrode, and wherein the MOS structure includes:
a first-conductivity-type source region exposed from the front surface of the semiconductor layer and configured to form a portion of a side surface of the at least one gate trench;
a second-conductivity-type channel region formed farther towards a rear surface of the semiconductor layer than the source region so as to make contact with the source region and configured to form a portion of the side surface of the at least one gate trench; and
a first-conductivity-type drain region formed farther towards the rear surface of the semiconductor layer than the channel region so as to make contact with the channel region and configured to form a bottom surface of the at least one gate trench, and
wherein the second terminal includes a source terminal connected to the source region.

### Claim 21 (depends on 1)

The device of claim 1, wherein the impurity regions include an IGBT structure forming a trench-gate-type IGBT (Insulated Gate Bipolar Transistor) that includes the gate electrode, and wherein the IGBT structure includes:
a first-conductivity-type emitter region exposed from the front surface of the semiconductor layer and configured to form a portion of a side surface of the at least one gate trench;
a second-conductivity-type base region formed farther towards a rear surface of the semiconductor layer than the emitter region so as to make contact with the emitter region and configured to form a portion of the side surface of the at least one gate trench; and
a first-conductivity-type collector region formed farther toward the rear surface of the semiconductor layer than the base region so as to make contact with the base region and configured to form a bottom surface of the at least one gate trench.

### Claim 22 (depends on 1)

The device of claim 1, wherein the impurity regions include an IGBT structure forming a trench-gate-type IGBT (Insulated Gate Bipolar Transistor) that includes the gate electrode, and wherein the IGBT structure includes:
a first-conductivity-type emitter region exposed from the front surface of the semiconductor layer and configured to form a portion of a side surface of the at least one gate trench;
a second-conductivity-type base region formed farther towards a rear surface of the semiconductor layer than the emitter region so as to make contact with the emitter region and configured to form a portion of the side surface of the at least one gate trench; and
a first-conductivity-type collector region formed at farther towards the rear surface of the semiconductor layer than the base region so as to make contact with the base region and configured to form a bottom surface of the at least one gate trench, and
wherein the second terminal includes an emitter terminal connected to the emitter region.

### Claim 23 (depends on 1)

The device of claim 1, wherein when seen in the plan view, all of the at least one isolation trench is disposed closer to a center of the device than a portion of the gate pad.

### Claim 24 (depends on 1)

The device of claim 1, wherein when seen in the plan view, the at least one isolation trench is disposed farther away from a center of the device than all of the gate pad.

### Claim 25

A semiconductor device, comprising:
a first-conductivity-type semiconductor layer including an active region in which a transistor having a plurality of impurity regions is formed, and a marginal region surrounding an outer periphery of the active region;
a second-conductivity-type channel layer formed between the active region and the marginal region so as to form a front surface of the semiconductor layer;
at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer;
a gate insulation film formed on an inner surface of the at least one gate trench;
a gate electrode formed inside the gate insulation film in the at least one gate trench;
at least one isolation trench arranged between the active region and the marginal region to surround the outer periphery of the active region, and formed to extend from the front surface of the semiconductor layer through the channel layer, the at least one isolation trench having a depth equal to a depth of the at least one gate trench;
an inter-layer insulation film formed on the semiconductor layer;
a first terminal formed on the inter-layer insulation film and connected to the gate electrode through the inter-layer insulation film;
a second terminal formed on the inter-layer insulation film and connected to one of the impurity regions of the transistor through the inter-layer insulation film;
a trench insulation film formed on an inner surface of the at least one isolation trench; and
a buried electrode formed inside the trench insulation film in the at least one isolation trench,
wherein the at least one isolation trench is positioned directly below the second terminal, and
wherein the second terminal is connected through the inter-layer insulation film to the buried electrode of the at least one isolation trench arranged directly below the second terminal.

### Claim 26

A semiconductor device, comprising:
a first-conductivity-type semiconductor layer including an active region in which a transistor having a plurality of impurity regions is formed, and a marginal region surrounding an outer periphery of the active region;
a second-conductivity-type channel layer formed between the active region and the marginal region so as to form a front surface of the semiconductor layer;
at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer;
a gate insulation film formed on an inner surface of the at least one gate trench;
a gate electrode formed inside the gate insulation film in the at least one gate trench;
at least one isolation trench arranged between the active region and the marginal region to surround the outer periphery of the active region, and formed to extend from the front surface of the semiconductor layer through the channel layer, the at least one isolation trench having a depth equal to a depth of the at least one gate trench;
an inter-layer insulation film formed on the semiconductor layer;
a first terminal formed on the inter-layer insulation film and connected to the gate electrode through the inter-layer insulation film;
a bonding wire; and
a second terminal formed on the inter-layer insulation film and connected to one of the impurity regions of the transistor through the inter-layer insulation film, wherein
the at least one isolation trench is positioned directly below the second terminal, and
the second terminal is formed to cover the active region, and
the first terminal includes a gate pad to which the bonding wire is connected, and when seen in a plan view,
the gate pad is disposed at an outer periphery of the second terminal, and
the at least one isolation trench bypasses the gate pad.