# US 8,772,825 B2 · Stacked semiconductor device and a method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,825 B2 - Document ID: US8772825B2 - Status: Granted - Kind: B2 - Application number: 13/618,479 - Filed: 2012-09-14 - Published: 2014-01-09 - Granted: 2014-07-08 - Earliest claimed: 2012-07-04 - Assignees: Phostek, Inc. - Applicants: Jinn Kong Sheu; Wei-Chih Lai - Inventors: Jinn Kong Sheu; Wei-Chih Lai - Web page: https://patentgrep.com/patent/US8772825B2 ## CPC - H10F 77/1246: {III-V nitrides, e.g. GaN} - H10F 10/10: having potential barriers - H10F 77/12485: {comprising nitride compounds, e.g. InGaN} - H10F 77/16: Material structures, e.g. crystalline structures, film structures or crystal plane orientations - H10H 20/811: having quantum effect structures or superlattices, e.g. tunnel junctions - H10H 20/813: having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies - Y02E 10/50: Photovoltaic [PV] energy - Y02E 10/544: Solar cells from Group III-V materials - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction. ## Claims ### Claim 1 A method of manufacturing a stacked semiconductor device, comprising; providing a first semiconductor unit having a first surface that is not a polar plane; forming at least one pit from the first surface, the pit having a second surface that lies at an angle relative to the first surface; forming a polarization enhanced tunnel junction on the second surface; and forming a second semiconductor unit above the tunnel junction, whereby the at least one pit enhances the polarization of the tunnel junction. ### Claim 2 (depends on 1) The method of claim 1, wherein the first surface is a non-polar plane or a semi-polar plane. ### Claim 3 (depends on 1) The method of claim 1, wherein the second surface is a polar plane or a semi-polar plane. ### Claim 4 (depends on 1) The method of claim 1, wherein the pit is formed by controlling a process temperature or a growth rate. ### Claim 5 (depends on 4) The method of claim 4, wherein the pit is formed at the process temperature in a range of 500-900° C. ### Claim 6 (depends on 4) The method of claim 4, wherein the pit is formed at the growth rate in a range of 1-6 m/h. ### Claim 7 (depends on 1) The method of claim 1, wherein the pit is formed by photolithography and etching techniques. ### Claim 8 (depends on 1) The method of claim 1, wherein the tunnel junction comprises an indium compound, and the method further increases a concentration of indium to enhance polarization in the tunnel junction. ### Claim 9 (depends on 1) The method of claim 1, wherein the second semiconductor unit is formed along the normal of a polar plane or a semi-polar plane. ### Claim 10 A stacked semiconductor device, comprising; a first semiconductor unit having a first surface that is not a polar plane; a second semiconductor unit formed above the first semiconductor unit; at least one pit formed from the first surface, the pit having a second surface that lies at an angle relative to the first surface; and a polarization enhanced tunnel junction formed on the second surface and in between the first semiconductor unit and the second semiconductor unit, whereby the at least one pit enhances the polarization of the tunnel junction. ### Claim 11 (depends on 10) The device of claim 10, wherein the first or the second semiconductor unit comprises a first doped layer, an active layer and a second doped layer, the first doped layer having conductivity opposite to conductivity of the second doped layer, and the active layer being interposed between the first doped layer and the second doped layer. ### Claim 12 (depends on 10) The device of claim 10, wherein the first or the second semiconductor unit comprises group III nitride. ### Claim 13 (depends on 10) The device of claim 10, wherein the first surface is a non-polar plane or a semi-polar plane. ### Claim 14 (depends on 10) The device of claim 10, wherein the second surface is a polar plane or a semi-polar plane. ### Claim 15 (depends on 10) The device of claim 10, wherein the first surface is an M plane and the second surface is a C plane or an R plane. ### Claim 16 (depends on 10) The device of claim 10, wherein the first surface is an A plane and the second surface is an R plane or a C plane. ### Claim 17 (depends on 10) The device of claim 10, wherein the first surface is an R plane and the second surface is a C plane. ### Claim 18 (depends on 10) The device of claim 10, wherein the pit has a depth less than or equal to 2 m, and larger than 10 nm. ### Claim 19 (depends on 10) The device of claim 10, wherein the tunnel junction is formed on the first surface. ### Claim 20 (depends on 10) The device of claim 10, wherein the tunnel junction comprises a super-lattice structure. ### Claim 21 (depends on 20) The device of claim 20, wherein the super-lattice structure comprises at least two sub-layers of distinct materials that are stacked alternately. ### Claim 22 (depends on 21) The device of claim 21, wherein each said sub-layer has a thickness less than or equal to 5 nm, and a thickness of the super-lattice structure is less than or equal to 10 nm. ### Claim 23 (depends on 21) The device of claim 21, wherein the super-lattice structure comprises group III nitride, and each said sub-layer comprises one, two or three elements of group III in accompanied with nitride, resulting in a binary compound, a ternary compound or a quaternary compound. ### Claim 24 (depends on 23) The device of claim 23, wherein the binary compound comprises indium nitride (InN), gallium nitride (GaN) or aluminum nitride (AlN); the ternary compound comprises indium gallium nitride (InxGa1-xN), indium aluminum nitride (InxAl1-xN), or aluminum gallium nitride (AlxGa1-xN); and the quaternary compound comprises indium aluminum gallium nitride (InxAlyGa1-x-yN). ### Claim 25 (depends on 10) The device of claim 10, wherein the tunnel junction comprises a three-layer structure that includes two doped layers and an insulating layer interposed between the two doped layers, one of the two doped layers having conductivity opposite to conductivity of the other doped layer, and the insulating layer including aluminum nitride (AlN) or silicon nitride (SiNx). ### Claim 26 (depends on 10) The device of claim 10, further comprising a buffer layer formed above the tunnel junction and filling up the pit. ### Claim 27 (depends on 10) The device of claim 10, wherein the second semiconductor unit has a surface that is a polar plane or a semi-polar plane.