# US 8,772,788 B2 · Semiconductor element and method of manufacturing thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,788 B2
- Document ID: US8772788B2
- Status: Granted
- Kind: B2
- Application number: 14/122,823
- Filed: 2012-04-23
- Published: 2014-04-24
- Granted: 2014-07-08
- Earliest claimed: 2011-05-30
- Assignees: Panasonic Corporation
- Applicants: Ryo Ikegami; Masao Uchida; Yuki Tomita; Masahiko Niwayama
- Inventors: Ryo Ikegami; Masao Uchida; Yuki Tomita; Masahiko Niwayama
- Web page: https://patentgrep.com/patent/US8772788B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/8325: {Silicon carbide}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/035: {using silicon carbide [SiC] technology}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device disclosed in the present application includes: a semiconductor substrate; a first silicon carbide semiconductor layer located on a principal surface of the semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type, and an impurity region of a first conductivity type; a trench provided in the first silicon carbide semiconductor layer so as to reach inside of the drift region; a second silicon carbide semiconductor layer of the first conductivity type located at least on a side surface of the trench so as to be in contact with the impurity region and the drift region; a gate insulating film; a gate electrode; a first ohmic electrode; and a second ohmic electrode. The body region includes a first body region which is in contact with the second silicon carbide semiconductor layer on the side surface of the trench, and a second body region which is in contact with the drift region and has a smaller average impurity concentration than the first body region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having a principal surface and a reverse surface;
a first silicon carbide semiconductor layer located on the principal surface of the semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type located on the drift region, and an impurity region of the first conductivity type located on the body region;
a trench provided in the first silicon carbide semiconductor layer, running through the body region so as to reach inside of the drift region;
a second silicon carbide semiconductor layer of the first conductivity type located at least on a side surface of the trench so as to be in contact with at least a portion of the drift region and at least a portion of the impurity region;
a gate insulating film located on the second silicon carbide semiconductor layer;
a gate electrode located on the gate insulating film;
a first ohmic electrode in contact with the impurity region; and
a second ohmic electrode located on the reverse surface of the semiconductor substrate;
the body region includes a first body region which is in contact with the impurity region and in contact with the second silicon carbide semiconductor layer on the side surface of the trench, and a second body region which is in contact with the drift region and in contact with the second silicon carbide semiconductor layer on the side surface of the trench and has a smaller average impurity concentration than the first body region;
potentials to be applied to the second ohmic electrode and the gate electrode with respect to the first ohmic electrode are Vds and Vgs, respectively, and a gate threshold voltage is Vth;
where Vgs≧Vth, a current flows from the second ohmic electrode to the first ohmic electrode through the second silicon carbide semiconductor layer; and
where 0 volt≦Vgs<Vth, a current flows from the first ohmic electrode to the second ohmic electrode through the second silicon carbide semiconductor layer before a current starts to flow from the body region to the drift region, as Vds becomes less than 0 volt.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first body region is not in contact with the drift region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second body region is further in contact with the impurity region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein:
the semiconductor device includes a plurality of unit cells;
each unit cell includes the semiconductor substrate, the first silicon carbide semiconductor layer, the trench, the second silicon carbide semiconductor layer, the gate insulating film, the gate electrode, the first ohmic electrode, and the second ohmic electrode,
wherein a width of the first body region of each unit cell in a direction parallel to the semiconductor substrate is equal to a width of the first body region of another unit cell, which is adjacent to said unit cell with the trench interposed therebetween, in a direction parallel to the semiconductor substrate.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first body region is defined in a self-aligned manner with respect to the trench.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the second body region is located under the first body region and is not in contact with the impurity region.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the second silicon carbide semiconductor layer and the body region are configured so that where 0 volt≦Vgs<Vth, a current flows from the first ohmic electrode to the second ohmic electrode through the second silicon carbide semiconductor layer before a current starts to flow from the body region to the drift region, as Vds becomes less than 0 volt.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the second silicon carbide semiconductor layer is an epitaxial layer.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein an average impurity concentration of the first body region is twice or more as high as an average impurity concentration of the second body region.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, further comprising an electric field relaxing region of the second conductivity type provided on a bottom surface of the trench.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, further comprising a contact region which is adjacent to the impurity region and is in contact with the second ohmic electrode and the second body region.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, the semiconductor device comprising:
a unit cell arrangement section including a plurality of unit cells arranged therein, each unit cell including the semiconductor substrate, the first silicon carbide semiconductor layer, the trench, the second silicon carbide semiconductor layer, the gate insulating film, the gate electrode, the first ohmic electrode, and the second ohmic electrode; and
a peripheral portion arranged outside the unit cell arrangement section as seen from a normal direction to the principal surface of the semiconductor substrate,
wherein the peripheral portion includes a ring region of the second conductivity type arranged in the first silicon carbide semiconductor layer so as to surround the unit cell arrangement section as seen from a normal direction to the principal surface of the semiconductor substrate, wherein an impurity concentration profile of the second conductivity type in a depth direction in the ring region is equal to an impurity concentration profile of the second conductivity type in a depth direction in the second body region of each unit cell.

### Claim 13

A semiconductor device comprising:
a semiconductor substrate having a principal surface and a reverse surface;
a first silicon carbide semiconductor layer located on the principal surface of the semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type located on the drift region, and an impurity region of the first conductivity type located on the body region;
a trench provided in the first silicon carbide semiconductor layer, running through the body region so as to reach inside of the drift region;
a second silicon carbide semiconductor layer of the first conductivity type located at least on a side surface of the trench so as to be in contact with at least a portion of the drift region and at least a portion of the impurity region;
a gate insulating film located on the second silicon carbide semiconductor layer;
a gate electrode located on the gate insulating film;
a first ohmic electrode in contact with the impurity region; and
a second ohmic electrode located on the reverse surface of the semiconductor substrate, wherein:
the body region includes a first body region which is in contact with the second silicon carbide semiconductor layer on the side surface of the trench, and a second body region which is in contact with the drift region and has a smaller average impurity concentration than the first body region;
the impurity region is in contact with the first body region and the second body region;
potentials to be applied to the second ohmic electrode and the gate electrode with respect to the first ohmic electrode are Vds and Vgs, respectively, and a gate threshold voltage is Vth;
where Vgs≧Vth, a current flows from the second ohmic electrode to the first ohmic electrode through the second silicon carbide semiconductor layer; and
where 0 volt≦Vgs<Vth, a current flows from the first ohmic electrode to the second ohmic electrode through the second silicon carbide semiconductor layer before a current starts to flow from the body region to the drift region, as Vds becomes less than 0 volt.

### Claim 14 (depends on 13)

The semiconductor device according to claim 13, wherein the first body region is not in contact with the drift region.

### Claim 15 (depends on 13)

The semiconductor device according to claim 13, wherein the first body region is further in contact with the drift region.

### Claim 16 (depends on 13)

The semiconductor device according to claim 13, wherein the second silicon carbide semiconductor layer is in contact with the first body region and the second body region on the side surface of the trench.

### Claim 17

A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a first silicon carbide semiconductor layer on a semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type and a second body region of a second conductivity type;
forming a mask on a partial region of a surface of the first silicon carbide semiconductor layer;
forming a first body region of the second conductivity type in the second body region of the first silicon carbide semiconductor layer by implanting an impurity using the mask;
forming a side wall on a side surface of the mask;
forming a trench running through the first body region so as to expose the drift region therethrough by etching the first silicon carbide semiconductor layer using the mask and the side wall;
activating the impurity region, the first body region and the second body region by performing a heat treatment on the first silicon carbide semiconductor layer; and
forming a second silicon carbide semiconductor layer so as to cover at least a side surface of the trench.

### Claim 18 (depends on 17)

The method for manufacturing a semiconductor device according to claim 17, wherein in the step of forming the first body region, the first body region which does not reach the drift region is formed.

### Claim 19 (depends on 17)

The method for manufacturing a semiconductor device according to claim 17, further comprising the steps of:
forming an impurity region by implanting an impurity into a surface portion of the second body region, between the step of forming the first silicon carbide semiconductor layer and the step of forming the mask, wherein:
in the step of forming the trench,
a trench running through the first body region and the impurity region is formed.

### Claim 20 (depends on 17)

The method for manufacturing a semiconductor device according to claim 17, wherein:
the step of forming the first silicon carbide semiconductor layer includes the step of:
forming the second body region while defining the drift region in an area other than the second body region by implanting an impurity into a surface portion of a silicon carbide semiconductor layer of the first conductivity type.

### Claim 21 (depends on 17)

The method for manufacturing a semiconductor device according to claim 17, wherein:
the semiconductor device includes a unit cell arrangement section including a plurality of unit cells arranged therein, and a peripheral portion arranged outside the unit cell arrangement section as seen from a normal direction to the principal surface of the semiconductor substrate;
in the peripheral portion, the first silicon carbide semiconductor layer includes a ring region of the second conductivity type arranged so as to surround the unit cell arrangement section as seen from a normal direction to the principal surface of the semiconductor substrate; and
the second body region and the ring region are formed in the same step.

### Claim 22 (depends on 19)

The method for manufacturing a semiconductor device according to claim 19, further comprising the step of forming a contact region in the impurity region and the second body region, before the step of forming the mask.

### Claim 23 (depends on 22)

The method for manufacturing a semiconductor device according to claim 22, further comprising the steps of:
forming a gate insulating film on the second silicon carbide semiconductor layer;
forming a gate electrode on the gate insulating film;
removing a portion of the gate insulating film and the second silicon carbide semiconductor layer so that a portion of the impurity region and the contact region are exposed;
forming a first ohmic electrode so as to be in contact with the exposed portion of the impurity region and the contact region; and
forming a second ohmic electrode so as to be in contact with a surface of the semiconductor substrate with which the first silicon carbide semiconductor layer is not in contact.