# US 8,772,769 B2 · Semiconductor device and method for manufacturing semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,769 B2
- Document ID: US8772769B2
- Status: Granted
- Kind: B2
- Application number: 13/646,076
- Filed: 2012-10-05
- Published: 2013-04-18
- Granted: 2014-07-08
- Earliest claimed: 2011-10-13
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US8772769B2

## CPC

- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10B 12/05: {Making the transistor}
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an Lov region is provided.

## Claims

### Claim 1

A semiconductor device comprising:
a source electrode layer and a drain electrode layer;
an oxide semiconductor layer comprising a first impurity region in contact with a side surface of the source electrode layer, a second impurity region in contact with a side surface of the drain electrode layer, and a channel formation region between the first impurity region and the second impurity region;
a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
a gate electrode layer over the gate insulating layer;
a first conductive sidewall layer in contact with one side surface of the gate electrode layer; and
a second conductive sidewall layer in contact with the other side surface of the gate electrode layer,
wherein a length of an upper surface of the oxide semiconductor layer is longer than a length of a lower surface of the oxide semiconductor layer,
wherein at least part of the first conductive sidewall layer overlaps with the source electrode layer with the gate insulating layer therebetween, and
wherein at least part of the second conductive sidewall layer overlaps with the drain electrode layer with the gate insulating layer therebetween.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises crystals whose c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one material selected from indium or zinc.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the oxide semiconductor layer further comprises at least one material selected from gallium, tin, hafnium, aluminum or zirconium.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first impurity region and the second impurity region comprise a material selected from phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, indium, titanium, or zinc.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an insulating layer over the gate insulating layer, the first conductive sidewall layer, the second conductive sidewall layer, and the gate electrode layer;
a first wiring layer electrically connected to the source electrode layer through a first opening in the insulating layer and the gate insulating layer; and
a second wiring layer electrically connected to the drain electrode layer through a second opening in the insulating layer and the gate insulating layer.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the insulating layer comprises aluminum oxide.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a stacked-layer structure.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device comprises a memory cell array including a plurality of memory cells.

### Claim 10

A semiconductor device comprising:
a first transistor comprising a first gate electrode layer; and
a second transistor comprising:
a source electrode layer and a drain electrode layer, the source electrode layer being in contact with the first gate electrode layer;
an oxide semiconductor layer comprising a first impurity region in contact with a side surface of the source electrode layer, a second impurity region in contact with a side surface of the drain electrode layer, and a channel formation region between the first impurity region and the second impurity region;
a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
a second gate electrode layer over the gate insulating layer;
a first conductive sidewall layer in contact with one side surface of the second gate electrode layer; and
a second conductive sidewall layer in contact with the other side surface of the second gate electrode layer,
wherein a length of an upper surface of the oxide semiconductor layer is longer than a length of a lower surface of the oxide semiconductor layer,
wherein at least part of the first conductive sidewall layer overlaps with the source electrode layer with the gate insulating layer therebetween, and
wherein at least part of the second conductive sidewall layer overlaps with the drain electrode layer with the gate insulating layer therebetween.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises crystals whose c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor layer.

### Claim 12 (depends on 10)

The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises at least one material selected from indium or zinc.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the oxide semiconductor layer further comprises at least one material selected from gallium, tin, hafnium, aluminum or zirconium.

### Claim 14 (depends on 10)

The semiconductor device according to claim 10, further comprising:
a second insulating layer over the gate insulating layer, the first conductive sidewall layer, the second conductive sidewall layer, and the second gate electrode layer;
an electrode layer electrically connected to the drain electrode layer through an opening in the gate insulating layer and the second insulating layer; and
a wiring over the second insulating layer, electrically connected to the drain electrode layer through the electrode layer.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14, wherein the second insulating layer comprises aluminum oxide.

### Claim 16 (depends on 10)

The semiconductor device according to claim 10, wherein the oxide semiconductor layer has a stacked-layer structure.

### Claim 17 (depends on 10)

The semiconductor device according to claim 10, wherein the semiconductor device comprises a memory cell array including a plurality of memory cells.

### Claim 18 (depends on 10)

The semiconductor device according to claim 10, wherein the first transistor is a silicon transistor.