# US 8,772,755 B2 · Directionally etched nanowire field effect transistors

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- Number: US 8,772,755 B2
- Document ID: US8772755B2
- Status: Granted
- Kind: B2
- Application number: 13/550,700
- Filed: 2012-07-17
- Published: 2012-11-08
- Granted: 2014-07-08
- Earliest claimed: 2010-05-10
- Assignees: International Business Machines Corporation
- Applicants: Sarunya Bangsaruntip; Guy M. Cohen; Jeffrey W. Sleight
- Inventors: Sarunya Bangsaruntip; Guy M. Cohen; Jeffrey W. Sleight
- Web page: https://patentgrep.com/patent/US8772755B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 86/01: Manufacture or treatment
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.

## Claims

### Claim 1

A nanowire field effect transistor (FET) device, comprising:
a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; and
a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a gate formed around a portion of the nanowire channel member.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first semiconductor layer includes silicon.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second semiconductor material includes SiGe.