# US 8,772,752 B2 · Semiconductor device

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- Number: US 8,772,752 B2
- Document ID: US8772752B2
- Status: Granted
- Kind: B2
- Application number: 13/477,373
- Filed: 2012-05-22
- Published: 2012-11-29
- Granted: 2014-07-08
- Earliest claimed: 2011-05-24
- Assignees: Semiconductor Energy Laboratory Co., Ltd.; Sharp Kabushiki Kaisha
- Applicants: Hidekazu Miyairi; Atsushi Hirose; Yoshitaka Yamamoto; Tomohiro Kimura
- Inventors: Hidekazu Miyairi; Atsushi Hirose; Yoshitaka Yamamoto; Tomohiro Kimura
- Web page: https://patentgrep.com/patent/US8772752B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6723: {having light shields}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 62/40: Crystalline structures
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An object is to prevent light leakage caused due to misregistration even when the width of a black matrix layer is not expanded to a designed value or larger. One embodiment of the present invention is a semiconductor device including a single-gate thin film transistor in which a first semiconductor layer is sandwiched between a bottom-gate electrode and a first black matrix layer. The first semiconductor layer and the first black matrix layer overlap with each other.

## Claims

### Claim 1

A semiconductor device comprising:
a first wiring; and
a second wiring intersecting the first wiring,
wherein a portion where the first wiring and the second wiring intersect each other includes a first insulating film formed over the first wiring, a first semiconductor layer formed over the first insulating film, a second insulating film formed over the first semiconductor layer, and the second wiring formed over the second insulating film,
wherein the second wiring is formed of a first black matrix layer, and
wherein the first black matrix layer and the first semiconductor layer overlap with each other.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the second wiring is electrically connected to one electrode of a source and a drain of a thin film transistor.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a third wiring through which the one electrode and the second wiring are electrically connected to each other; and
a second semiconductor layer arranged between the third wiring and a bottom-gate electrode of the thin film transistor,
wherein the third wiring is formed of a second black matrix layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a signal line sharing circuit which divides one signal into a plurality of signals and supplies the plurality of signals to a plurality of wirings,
wherein any of the plurality of signals into which the one signal is divided by the signal line sharing circuit is supplied to the first wiring or the second wiring.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a signal line sharing circuit including:
a first transistor;
a second transistor;
a third transistor;
a fourth wiring into which one signal is input and which is electrically connected to one first electrode of a source and a drain of the first transistor, one second electrode of a source and a drain of the second transistor, and one third electrode of a source and a drain of the third transistor;
a fifth wiring which is electrically connected to a gate electrode of the first transistor and to which a signal for controlling the first transistor is input;
a sixth wiring which is electrically connected to a gate electrode of the second transistor and to which a signal for controlling the second transistor is input; and
a seventh wiring which is electrically connected to a gate electrode of the third transistor and to which a signal for controlling the third transistor is input,
wherein the first wiring or the second wiring is electrically connected to any of the other first electrode of the source and the drain of the first transistor, the other second electrode of the source and the drain of the second transistor, and the other third electrode of the source and the drain of the third transistor.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the first semiconductor layer comprises a microcrystalline silicon region.