# US 8,772,751 B2 · Variable resistance semiconductor memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,751 B2
- Document ID: US8772751B2
- Status: Granted
- Kind: B2
- Application number: 13/234,388
- Filed: 2011-09-16
- Published: 2012-09-27
- Granted: 2014-07-08
- Earliest claimed: 2011-03-22
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Akira Takashima; Daisuke Matsushita; Takashi Yamauchi; Yuuichi Kamimuta; Hidenori Miyagawa
- Inventors: Akira Takashima; Daisuke Matsushita; Takashi Yamauchi; Yuuichi Kamimuta; Hidenori Miyagawa
- Web page: https://patentgrep.com/patent/US8772751B2

## CPC

- H10N 70/20: Multistable switching devices, e.g. memristors
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- G11C 2213/33: Material including silicon
- G11C 2213/52: Structure characterized by the electrode material, shape, etc.
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0≦x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.

## Claims

### Claim 1

A memory device comprising:
a first electrode of a resistance change element which comprises a crystallized SixGe1-x layer (0≦x<1);
a second electrode of a resistance change element which comprises a metal element;
a variable resistance part between the first and second electrode, the part comprising an amorphous Si layer;
a control circuit controlling a filament in the amorphous Si layer, the filament comprising the metal element, and
an inter layer between the SixGe1-x layer and the amorphous Si layer, the inter layer isolating crystal structures of the SixGe1-x layer and the amorphous Si layer from each other.

### Claim 2 (depends on 1)

The device of claim 1,
wherein the SixGe1-x layer has a polycrystalline structure.

### Claim 3 (depends on 1)

The device of claim 1,
wherein the SixGe1-x layer comprises boron.

### Claim 4 (depends on 1)

The device of claim 1,
wherein the first electrode comprises layers, and one of the layers is the SixGe1-x layer.

### Claim 5 (depends on 1)

The device of claim 1,
wherein the metal element is one selected from the group of Ag, Fe, Co, Ni, Cu, Ag, Au, and Zn.

### Claim 6 (depends on 1)

The device of claim 1,
wherein the amorphous Si layer is nondoped amorphous Si.

### Claim 7 (depends on 1)

The device of claim 1,
wherein the first electrode comprises a crystallized Si layer between the SixGe1-x layer and the inter layer.

### Claim 8 (depends on 1)

The device of claim 1,
wherein a thickness of the inter layer is within a range of 0.3 to 3 nm.

### Claim 9 (depends on 1)

The device of claim 1, further comprising:
an inter layer between the SixGe1-x layer and the amorphous Si layer, the inter layer is one selected from the group of a silicon oxide, a silicon oxynitride and a silicon.

### Claim 10 (depends on 1)

The device of claim 1, further comprising:
an inter layer between the SixGe1-x layer and the amorphous Si layer, the inter layer is one selected from the group of a silicon oxide, a silicon oxynitride, a silicon nitride, an alumina, a hafnium oxide, a zirconium oxide, a titanium oxide, a lanthanum oxide, a praseodymium oxide and a dysprosium oxide.

### Claim 11 (depends on 1)

The device of claim 1, further comprising:
an inter layer between the SixGe1-x layer and the amorphous Si layer, the inter layer is one selected from the group of a hafnium silicon oxide, a zirconium silicon oxide, a titanium silicon oxide, a lanthanum silicon oxide, a praseodymium silicon oxide, a dysprosium silicon oxide, a hafnium aluminum oxide, a zirconium aluminum oxide, a titanium aluminum oxide, a lanthanum aluminum oxide, a praseodymium aluminum oxide, a dysprosium aluminum oxide, a lanthanum aluminum silicon oxide, a praseodymium aluminum silicon oxide, a dysprosium aluminum silicon oxide, a hafnium silicon oxynitride, a zirconium silicon oxynitride and a titanium silicon oxynitride.

### Claim 12

A memory device comprising:
a first electrode including a crystallized SixGe1-x layer (0≦x<1);
a second electrode including a metal element;
a variable resistance part between the first and second electrode, the part including an amorphous Si layer; and
a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element,
wherein the SixGe1-x layer (except for x=0) has a concentration gradient in its composition in which a Si concentration is highest at a portion closest to the amorphous Si.

### Claim 13 (depends on 1)

The device of claim 1, further comprising:
a first conductive line which is connected to the first electrode and extends in a first direction; and
a second conductive line which is connected to the second electrode and extends in a second direction which intersects the first direction.

### Claim 14 (depends on 1)

The device of claim 1, further comprising:
a first conductive line which is connected to the first electrode and extends in a first direction;
a second conductive line which is connected to the second electrode and extends in a second direction which intersects the first direction; and
a rectifying unit which is disposed between the first and second conductive lines and connected serially to the variable resistance part.

### Claim 15 (depends on 1)

The device of claim 1, further comprising:
a conductive line which is connected to one of the first and second electrodes and extends in a first direction; and
a FET of which a source/drain is connected to the other one of the first and second electrodes and a gate of the FET extends in a second direction which intersects the first direction.

### Claim 16 (depends on 1)

A method of executing a set operation and a reset operation of the device of claim 1,
the set operation comprising:
making a voltage of the second electrode to a value higher than a voltage of the first electrode; and
increasing current between the first and second electrodes,
the reset operation comprising:
making a voltage of the first electrode to a value higher than a voltage of the second electrode.

### Claim 17 (depends on 1)

A method of manufacturing the device of claim 1, comprising:
forming an amorphous SixGe1-x layer (0≦x<1);
changing the amorphous SixGe1-x layer to the crystallized SixGe1-x layer of the claim 1 by an anneal in a temperature lower than a temperature in which Si is crystallized; and
forming the amorphous Si layer on the crystallized SixGe1-x layer.

### Claim 18 (depends on 1)

A method of manufacturing the device of claim 1, comprising:
forming an amorphous SixGe1-x layer (0≦x<1);
forming the inter layer on the amorphous SixGe1-x layer;
changing the amorphous SixGe1-x layer to the crystallized SixGe1-x layer of the claim 1 by an anneal in a temperature lower than a temperature in which Si is crystallized; and
forming the amorphous Si layer on the inter layer.

### Claim 19 (depends on 7)

A method of manufacturing the device of claim 7, comprising:
forming an amorphous SixGe1-x layer (0≦x<1);
forming an amorphous Si layer on the amorphous SixGe1-x layer;
changing the amorphous SixGe1-x layer and the amorphous Si layer to the crystallized SixGe1-x layer and the crystallized Si layer by an anneal in a temperature lower than 600° C.;
forming the inter layer on the crystallized Si layer; and
forming the amorphous Si layer on the inter layer.