# US 8,772,749 B2 · Bottom electrodes for use with metal oxide resistivity switching layers

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- Number: US 8,772,749 B2
- Document ID: US8772749B2
- Status: Granted
- Kind: B2
- Application number: 13/047,020
- Filed: 2011-03-14
- Published: 2011-09-22
- Granted: 2014-07-08
- Earliest claimed: 2010-03-16
- Assignees: SanDisk 3D LLC
- Applicants: Deepak Chandra Sekar; Franz Kreupl; Raghuveer S. Makala
- Inventors: Deepak Chandra Sekar; Franz Kreupl; Raghuveer S. Makala
- Web page: https://patentgrep.com/patent/US8772749B2

## CPC

- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/883: {Oxides or nitrides}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.

## Claims

### Claim 1

A device comprising:
a metal-insulator-metal (MIM) stack comprising:
a first conductive layer comprising a silicon-germanium (SiGe) alloy;
a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and
a second conductive layer formed above the resistivity-switching layer; and
a diode coupled to and disposed above or below the MIM stack.

### Claim 2 (depends on 1)

The device of claim 1 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.

### Claim 3 (depends on 1)

The device of claim 1 wherein the first conductive layer has a thickness of about 2-100 nanometers.

### Claim 4 (depends on 1)

The device of claim 1 wherein the metal oxide layer comprises one or more of HfOX, ZrOX, NiOX, TiOX, TaOX, NbOX or AlXOY.

### Claim 5 (depends on 1)

The device of claim 1 wherein the second conductive layer comprises titanium nitride.

### Claim 6 (depends on 5)

The device of claim 5 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.

### Claim 7 (depends on 1)

A memory cell comprising:
the device of claim 1.

### Claim 8 (depends on 7)

The memory cell of claim 7 wherein the diode comprises a vertical polysilicon diode coupled in series with the MIM stack.

### Claim 9 (depends on 7)

The memory cell of claim 7 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.

### Claim 10 (depends on 7)

The memory cell of claim 7 wherein the first conductive layer has a thickness of about 2-100 nanometers.

### Claim 11 (depends on 7)

The memory cell of claim 7 wherein the metal oxide layer comprises one or more of HfOX, ZrOX, NiOX, TiOX, TaOX, NbOX or AlXOY.

### Claim 12 (depends on 7)

The memory cell of claim 7 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.

### Claim 13

A method of forming a device, the method comprising:
forming a metal-insulator-metal (MIM) stack comprising:
forming a first conductive layer comprising a silicon-germanium (SiGe) alloy;
forming a resistivity-switching layer comprising a metal oxide layer above the first conductive layer; and
forming a second conductive layer above the resistivity-switching layer; and
forming a diode coupled to and disposed above or below the MIM stack.

### Claim 14 (depends on 13)

The method of claim 13 wherein the first conductive layer is formed at a temperature of not more than about 600° C.

### Claim 15 (depends on 13)

The method of claim 13 wherein the first conductive layer is formed at a temperature of not more than about 550° C.

### Claim 16 (depends on 13)

The method of claim 13 wherein the first conductive layer is formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

### Claim 17 (depends on 13)

The method of claim 13 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.

### Claim 18 (depends on 13)

The method of claim 13 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.

### Claim 19 (depends on 13)

The method of claim 13 wherein the metal oxide layer comprises one or more of HfOX, ZrOX, NiOX, TiOX, TaOX, NbOX or AlXOY.

### Claim 20

A method of forming a memory cell comprising:
forming a metal-insulator-metal (MIM) stack having:
a first conductive layer comprising a silicon-germanium (SiGe) alloy;
a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and
a second conductive layer formed above the resistivity-switching layer; and
forming a steering element coupled to and disposed above or below the MIM stack.

### Claim 21 (depends on 20)

The method of claim 20 wherein the first conductive layer is formed at a temperature of not more than about 600° C.

### Claim 22 (depends on 20)

The method of claim 20 wherein the first conductive layer is formed at a temperature of not more than about 550° C.

### Claim 23 (depends on 20)

The method of claim 20 wherein the first conductive layer is formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

### Claim 24 (depends on 20)

The method of claim 20 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.

### Claim 25 (depends on 20)

The method of claim 20 wherein the metal oxide layer comprises one or more of HfOX, ZrOX, NiOX, TiOX, TaOX, NbOX or AlXOY.