# US 8,772,746 B2 · Semiconductor memory device

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- Number: US 8,772,746 B2
- Document ID: US8772746B2
- Status: Granted
- Kind: B2
- Application number: 13/349,653
- Filed: 2012-01-13
- Published: 2012-08-23
- Granted: 2014-07-08
- Earliest claimed: 2011-02-21
- Assignees: Hitachi, Ltd.
- Applicants: Masaharu Kinoshita; Yoshitaka Sasago; Takashi Kobayashi
- Inventors: Masaharu Kinoshita; Yoshitaka Sasago; Takashi Kobayashi
- Web page: https://patentgrep.com/patent/US8772746B2

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/82: {the switching components having a common active material layer}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a plurality of first word lines formed above a semiconductor substrate and extending in a first direction parallel to the surface of the semiconductor substrate;
a first gate insulating film formed above each of the plurality of first word lines;
a first channel formed above the first gate insulating film, crossing the first direction, and extending in a second direction parallel to the surface of the semiconductor substrate;
a first resistance change element formed above the first channel and extending in the second direction, in which a portion of the first channel and a portion of the first resistance change element are disposed above each of the plurality of the first word lines respectively; and
a third word line formed above the semiconductor substrate and extending in the first direction,
wherein the first gate insulating film and the first channel are formed above the third word line, and
wherein the first resistance change element is not formed above the third word line.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the plurality of the word lines and the first channel each comprise a polysilicon layer.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first channel has a lamination structure comprising a plurality of polysilicon layers.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first gate insulating film comprises silicon oxide.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first resistive change material comprises a phase change material.

### Claim 6 (depends on 5)

The semiconductor memory device according to claim 5, wherein the phase change material is Ge2Sb2Te5.