# US 8,772,648 B2 · Method for manufacturing printed wiring board and printed wiring board > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,648 B2 - Document ID: US8772648B2 - Status: Granted - Kind: B2 - Application number: 13/442,921 - Filed: 2012-04-10 - Published: 2012-08-09 - Granted: 2014-07-08 - Earliest claimed: 2008-09-30 - Assignees: Ibiden Co., Ltd. - Applicants: Toshiki Furutani; Takeshi Furusawa - Inventors: Toshiki Furutani; Takeshi Furusawa - Web page: https://patentgrep.com/patent/US8772648B2 ## CPC - H05K 1/113: {Via provided in pad; Pad over filled via} - H05K 3/428: {initial plating of through-holes in substrates having a metal pattern} - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H05K 1/0269: {for visual or optical inspection} - H05K 3/0035: {of blind holes, i.e. having a metal layer at the bottom} - H05K 3/107: {by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence)} - H05K 3/205: {using a pattern electroplated or electroformed on a metallic carrier} - H05K 3/421: {Blind plated via connections (H05K3/422, H05K3/423 and H05K3/425 take precedence)} - H05K 3/423: {characterised by electroplating method} - H05K 2201/0394: Conductor crossing over a hole in the substrate or a gap between two separate substrate parts - H05K 2201/09481: Via in pad; Pad over filled via - H05K 2201/09563: Metal filled via - H05K 2203/0542: Continuous temporary metal layer over metal pattern - H05K 2203/166: Alignment or registration; Control of registration - H05K 2203/167: Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment - H10W 70/685: comprising multiple insulating layers - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y10T 29/49117: Conductor or circuit manufacturing - Y10T 29/49124: On flat or curved insulated base, e.g., printed circuit, etc. - Y10T 29/49155: Manufacturing circuit on or in base - Y10T 29/49165: by forming conductive walled aperture in base - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections. ## Claims ### Claim 1 A printed wiring board, comprising: a single insulating layer comprising an insulative resin base material and having a first surface and a second surface opposite the first surface; first and second conductive circuits embedded in the first surface and the second surface of the insulative resin base material respectively; a filled via comprising: an electroless plated film formed on an inner wall of a via opening that reaches from the first surface of the single insulating layer to the second conductive circuit embedded in the second surface of the single insulating layer, and an electrolytic plated film filled in the via opening having the electroless plated film; a first solder resist layer formed on the first surface and the first conductive circuit, the first solder resist layer having a first opening which exposes the filled via; a second solder resist layer formed on the second surface and the second conductive circuit, the second solder resist layer having a second opening which exposes the second conductive circuit which is connected to the filled via; first solder bump formed on the filled via which is exposed from the first opening in the first solder resist layer; and second solder bump formed on the second conductor circuit which is exposed from the second opening in the second solder resist layer such that the filled via is sandwiched between the first and second solder bumps. ### Claim 2 (depends on 1) The printed wiring board according to claim 1, wherein the filled via comprises an electroless plated film formed directly on the inner wall of the via opening and an electrolytic plated film formed directly on the electroless plated film. ### Claim 3 (depends on 1) The printed wiring board according to claim 1, wherein the second surface is a surface on which an electronic component is mounted. ### Claim 4 (depends on 1) The printed wiring board according to claim 1, wherein the filled via is filled such that a surface of the electrolytic plated film is on substantially a same level with a planar surface of the electroless plating film. ### Claim 5 (depends on 1) The printed wiring board of claim 1, wherein the first opening partially exposes a top surface of the filled via. ### Claim 6 (depends on 5) The printed wiring board of claim 5, wherein said top surface of the filled via is dented with respect to said first surface of the single insulating layer. ### Claim 7 (depends on 6) The printed wiring board of claim 6, wherein said second surface of the single insulating layer has greater flatness than said first surface single insulating layer. ### Claim 8 A printed wiring board, comprising: a single insulating layer comprising an insulative resin base material and having a first surface and a second surface opposite the first surface; first and second conductive circuits embedded in the first surface and the second surface of the insulative resin base material respectively; a filled via comprising: an electroless plated film formed on an inner wall of a via opening that reaches from the second surface of the single insulating layer to the first conductive circuit embedded in the first surface of the single insulating layer, and an electrolytic plated film filled in the via opening having the electroless plated film; a first solder resist layer formed on the first surface and the first conductive circuit, the first solder resist layer having a first opening which exposes the first conductive circuit which is connected to the filled via; a second solder resist layer formed on the second surface and the second conductive circuit, the second solder resist layer having a second opening which exposes the filled via; a first solder bump formed on the first conductor circuit which is exposed from the first opening in the first solder resist layer; and a second solder bump formed on the filled via which is exposed from the second opening in the second solder resist layer such that the filled via is sandwiched between the first and second solder bumps. ### Claim 9 (depends on 8) The printed wiring board according to claim 8, wherein the filled via comprises an electroless plated film formed directly on the inner wall of the via opening and an electrolytic plated film formed directly on the electroless plated film. ### Claim 10 (depends on 8) The printed wiring board according to claim 8, wherein the second surface is a surface on which an electronic component is mounted. ### Claim 11 (depends on 8) The printed wiring board according to claim 8, wherein the filled via is filled such that a surface of the electrolytic plated film is on substantially a same level with a planar surface of the electroless plating film. ### Claim 12 (depends on 8) The printed wiring board of claim 8, wherein the second opening partially exposes a top surface of the filled via. ### Claim 13 (depends on 12) The printed wiring board of claim 12, wherein said top surface of the filled via is dented with respect to said second surface of the single insulating layer. ### Claim 14 (depends on 13) The printed wiring board of claim 13, wherein said first surface of the single insulating layer has greater flatness than said second surface single insulating layer.