# US 8,772,643 B2 · Multilayer wiring substrate, and method of manufacturing the same

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- Number: US 8,772,643 B2
- Document ID: US8772643B2
- Status: Granted
- Kind: B2
- Application number: 13/028,545
- Filed: 2011-02-16
- Published: 2011-08-18
- Granted: 2014-07-08
- Earliest claimed: 2010-02-16
- Assignees: Ngk Spark Plug Co., Ltd.
- Applicants: Shinnosuke Maeda; Tetsuo Suzuki; Satoshi Hirano
- Inventors: Shinnosuke Maeda; Tetsuo Suzuki; Satoshi Hirano
- Web page: https://patentgrep.com/patent/US8772643B2

## CPC

- H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil}
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 3/205: {using a pattern electroplated or electroformed on a metallic carrier}
- H05K 2201/09745: Recess in conductor, e.g. in pad or in metallic substrate
- H05K 2201/099: Coating over pads, e.g. solder resist partly over pads
- H05K 2203/0361: Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
- H05K 2203/0369: Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
- H05K 2203/0588: Second resist used as pattern over first resist
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- Y10T 29/302: Clad or other composite foil or thin metal making
- Y10T 29/49117: Conductor or circuit manufacturing
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

## Claims

### Claim 1

A multilayer wiring substrate comprising a laminate structure in which a plurality of resin insulation layers made primarily of a same resin insulation material, and a plurality of conductive layers are laminated alternately in multilayer arrangement, a plurality of first-main-surface-side connection terminals being disposed on a first main surface side of the laminate structure, a plurality of second-main-surface-side connection terminals being disposed on a second main surface side of the laminate structure, the plurality of conductive layers being formed in the plurality of resin insulation layers and interconnected by means of via conductors whose diameters increase toward the first main surface side of the laminate structure or the second main surface side of the laminate structure, wherein:
the plurality of resin insulation layers are formed of a hardened resin insulation material that is not photocurable;
a plurality of first openings are formed in an outermost resin insulation layer on the first main surface side of the laminate structure;
the plurality of first-main-surface-side connection terminals include terminal outer surfaces and are disposed to correspond to the plurality of first openings, and peripheral portions of the terminal outer surfaces are covered by the outermost resin insulation layer on the first main surface side of the laminate structure;
a plurality of second openings are formed in an outermost resin insulation layer on the second main surface side of the laminate structure;
the plurality of second-main-surface-side connection terminals are disposed to correspond to the plurality of second openings and include terminal inner surfaces and terminal outer surfaces, the terminal inner surfaces including a peripheral edge that is rounded and peripheral portions of the terminal outer surfaces are covered by the outermost resin insulation layer on the second main surface side of the laminate structure;
each of the plurality of second-main-surface-side connection terminals includes a copper layer having a concave portion that extends across the entire portion of the terminal outer surfaces that are exposed from the plurality of second opening; and
a plating layer covering the concave portion of the copper layer.

### Claim 2 (depends on 1)

The multilayer wiring substrate according to claim 1, wherein a deepest portion of the concave portion of each of the terminal outer surfaces of the plurality of second-main-surface-side connection terminals is located on an interior side in relation to the peripheral portion of each of the terminal outer surfaces of the plurality of second-main-surface-side connection terminals.

### Claim 3 (depends on 1)

The multilayer wiring substrate according to claim 1, wherein the first-main-surface-side connection terminals include IC-chip connection terminals, to which an IC chip is to be connected, and passive-component connection terminals, to which a passive component is to be connected and which are greater in area than the IC-chip connection terminals; and
the second-main-surface-side connection terminals include motherboard connection terminals, to which a motherboard is to be connected and which are greater in area than the IC-chip connection terminals and the passive-component connection terminals.

### Claim 4 (depends on 1)

The multilayer wiring substrate according to claim 1, wherein the first-main-surface-side connection terminals include IC-chip connection terminals, to which an IC chip is to be connected; and
the second-main-surface-side connection terminals include passive-component connection terminals, to which a passive component is to be connected and which are greater in area than the IC-chip connection terminals, and motherboard connection terminals, to which a motherboard is to be connected and which are greater in area than the IC-chip connection terminals and the passive-component connection terminals.

### Claim 5 (depends on 1)

The multilayer wiring substrate according to claim 1, wherein the via conductors formed in the plurality of resin insulation layers are shaped such that their diameters increase in a direction from the second main surface side to the first main surface side.

### Claim 6 (depends on 1)

The multilayer wiring substrate according to claim 1,
wherein the plurality of second-main-surface-side connection terminals include motherboard connection terminals and the plurality of first-main-surface-side connection terminals include IC-chip connection terminals and passive-component connection terminals, and
wherein the motherboard connection terminals, the IC-chip connection terminals, and the passive-component connection terminals comprise a copper layer covered with a plating layer comprised of a material other than copper.

### Claim 7 (depends on 1)

The multilayer wiring substrate according to claim 1, wherein each of the terminal outer surfaces of the plurality of second-main-surface-side connection terminals is formed such that a deepest portion of the concave portion is located on an interior side in relation to an inner main surface of the outermost resin insulation layer on the second main surface side of the laminate structure.