# US 8,772,183 B2 · Method of forming an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,183 B2 - Document ID: US8772183B2 - Status: Granted - Kind: B2 - Application number: 13/277,552 - Filed: 2011-10-20 - Published: 2013-04-25 - Granted: 2014-07-08 - Earliest claimed: 2011-10-20 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Tzu-Yen Hsieh; Chang Ming-Ching; Chun-Hung Lee; Yih-Ann Lin; De-Fang Chen; Chao-Cheng Chen - Inventors: Tzu-Yen Hsieh; Chang Ming-Ching; Chun-Hung Lee; Yih-Ann Lin; De-Fang Chen; Chao-Cheng Chen - Web page: https://patentgrep.com/patent/US8772183B2 ## CPC - H10P 76/4088: {Processes for improving the resolution of the masks} - H10P 30/204: {into Group IV semiconductors} - H10P 30/208: {of electrically inactive species} - H10P 30/22: using masks - H10P 32/302: {Doping polycrystalline silicon or amorphous silicon layers} - H10P 50/28: of insulating materials - H10P 50/667: {by liquid etching only} - H10P 50/71: {using masks for conductive or resistive materials} - H10P 50/73: {using masks for insulating materials} - H10P 76/2043: {using an anti-reflective coating} - H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1. ## Claims ### Claim 1 A method of forming an integrated circuit, the method comprising: providing a first material layer; forming a second material layer on the first material layer; forming a patterned mask layer having a plurality of first features with a first pitch P1 on the second material layer; patterning the second material layer by using the patterned mask layer as a mask to form the first features in the second material layer and expose a portion of a top surface of the first material layer; trimming the patterned mask layer after patterning the second material layer to form a trimmed patterned mask layer; introducing a plurality of dopants into the second material layer not covered by the trimmed patterned mask layer to form doped regions with a second pitch P2, wherein the second pitch P2 is smaller than the first pitch P1; removing the trimmed patterned mask layer to expose un-doped regions in the second material layer; selectively removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions in the second material layer. ### Claim 2 (depends on 1) The method of claim 1, wherein the second pitch P2 is substantially one-half of the first pitch P1. ### Claim 3 (depends on 1) The method of claim 1, wherein the step of selectively removing comprises removing the un-doped regions with an etchant, wherein the etchant has a higher etching removal rate for the un-doped regions than for the doped regions. ### Claim 4 (depends on 1) The method of claim 1, wherein the second material layer comprises a polysilicon layer, a single crystalline silicon layer, or an amorphous silicon layer. ### Claim 5 (depends on 4) The method of claim 4, wherein the step of selectively removing comprises removing the un-doped regions with an etchant, the etchant comprising tetramethyl ammonium hydroxide (TMAH), tetrabutylphosphonium hydroxide, tetraphenylarsonium hydroxide, KOH, NaOH or NH4OH. ### Claim 6 (depends on 4) The method of claim 4, wherein the dopants comprise As, P, B, C, N, Si, Ge or BF2. ### Claim 7 (depends on 4) The method of claim 4, wherein a dosage of the dopants is substantially higher than 1E15 ion/cm2. ### Claim 8 (depends on 1) The method of claim 1, wherein step of introducing the plurality of dopants comprises substantially vertically implanting the plurality of dopants into the second material layer. ### Claim 9 (depends on 1) The method of claim 1, further comprising etching the first material layer by using the plurality of second features as a mask. ### Claim 10 (depends on 1) The method of claim 1, wherein sidewalls of each second feature are vertically aligned with corresponding sidewalls of the trimmed patterned mask layer. ### Claim 11 (depends on 1) The method of claim 1, wherein sidewalls of each second feature are vertically aligned with corresponding sidewalls of the trimmed patterned mask layer. ### Claim 12 (depends on 1) The method of claim 1, wherein the step of selectively removing comprises removing the un-doped silicon layer with an etchant, wherein the etchant has a higher etching removal rate for the un-doped silicon layer than for the doped silicon layer as a mask. ### Claim 13 A method of forming an integrated circuit, the method comprising: providing a first material layer; forming a second material layer on the first material layer; forming a patterned mask layer having a plurality of first features with a first pitch P1 on the second material layer, wherein each first feature has a first space S1 to adjacent first features; etching the second material layer by using the patterned mask layer as a mask to form the first features in the second material layer and expose a portion of a top surface of the first material layer; widening the first space S1 in the patterned mask layer to a space ST; after widening the first space S1, implanting a plurality of dopants into the second material layer not covered by the patterned mask layer; removing the patterned mask layer to expose un-doped second material layer; selectively removing the un-doped second material layer to form a plurality of second features with a second pitch P2 in the second material layer, wherein the second pitch P2 is substantially one-half of the first pitch P1. ### Claim 14 (depends on 13) The method of claim 13, wherein the second material layer comprises a polysilicon layer, a single crystalline silicon layer or an amorphous silicon layer. ### Claim 15 (depends on 14) The method of claim 14, wherein the etchant comprises tetramethyl ammonium hydroxide (TMAH), tetrabutylphosphonium hydroxide, tetraphenylarsonium hydroxide, KOH, NaOH or NH4OH. ### Claim 16 (depends on 14) The method of claim 14, wherein a dosage of the dopants is substantially higher than 1E15 ion/cm2. ### Claim 17 (depends on 13) The method of claim 13, wherein the step of selectively removing comprises removing the un-doped second material layer with an etchant, wherein the etchant has a higher etching removal rate for the un-doped second material layer than for the doped second material layer. ### Claim 18 (depends on 13) The method of claim 13, wherein step of introducing the plurality of dopants comprises substantially vertically implanting the plurality of dopants into the second material layer. ### Claim 19 (depends on 13) The method of claim 13, further comprising etching the first material layer by using the plurality of second features as a mask. ### Claim 20 A method of forming an integrated circuit, the method comprising: providing a first material layer; forming a silicon layer on the first material layer; forming a patterned mask layer having a plurality of first features with a first pitch P1 on the silicon layer; patterning the silicon layer by using the patterned mask layer as a mask to form the first features in the silicon layer and expose a portion of a top surface of the first material layer; trimming the patterned mask layer after patterning the silicon layer to form a trimmed patterned mask layer; substantially vertically implanting a plurality of dopants into the silicon layer not covered by the trimmed patterned mask layer; removing the trimmed patterned mask layer to expose an un-doped silicon layer; selectively removing the un-doped silicon layer with an etchant to form a plurality of second features with a second pitch P2 in the silicon layer, wherein the second pitch P2 is smaller than the first pitch P1.