# US 8,772,169 B2 · Technique for controlling trench profile in semiconductor structures

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- Number: US 8,772,169 B2
- Document ID: US8772169B2
- Status: Granted
- Kind: B2
- Application number: 12/109,302
- Filed: 2008-04-24
- Published: 2009-10-29
- Granted: 2014-07-08
- Earliest claimed: 2008-04-24
- Assignees: Fairchild Semiconductor Corporation
- Applicants: Hui Chen; Qi Wang; Briant Harward; James Pan
- Inventors: Hui Chen; Qi Wang; Briant Harward; James Pan
- Web page: https://patentgrep.com/patent/US8772169B2

## Abstract

A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
forming a single masking layer on a semiconductor region;
forming a trench in the semiconductor region using an opening in the single masking layer, the trench having a sidewall having a first slope and defining a mesa region adjacent to the trench;
removing completely the single masking layer; and
performing a bevel etch to taper the sidewall of the trench so that the sidewall has a second slope that is less than the first slope.

### Claim 2 (depends on 1)

The method of claim 1, wherein after the bevel etch, a width of the trench gradually decreases from a top of the trench toward a bottom of the trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein the trench is a first trench, the method further comprising:
forming a second trench, the mesa region being disposed between the first trench and the second trench, the bevel etch removing a layer of the semiconductor region along a top surface of the mesa region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the trench is performed using a plasma dry etch.

### Claim 5 (depends on 1)

The method of claim 1, wherein the bevel etch is performed using at least one fluorine-containing gas and at least one inert gas.

### Claim 6 (depends on 5)

The method of claim 5, wherein the at least one fluorine-containing gas includes one or both of SF6 and NF3, and the at least one inert gas includes one or more of N2, He, Ar, and Xe.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second slope is dependent on a conduction loss value L and a surface reaction loss value S.

### Claim 8 (depends on 1)

The method of claim 1, wherein an angle of the second slope of the trench θ is provided by:
tan
⁢
⁢
θ
=
1
t
·
C
·
Φ
⁡
(
0
)
·
1
S
⁡
(
L
+
S
)
,
wherein t represents etch time, C is an etch rate constant, and Φ(0) represents flux of an etchant species at a trench depth “0”.

### Claim 9 (depends on 8)

The method of claim 8, wherein a conduction loss value L is proportional to 1-K, wherein K is transmission probability, and a surface reaction loss value S is proportional to surface reaction probability.

### Claim 10 (depends on 1)

The method of claim 1, wherein the bevel etch does not widen a width along a bottom of the trench.

### Claim 11 (depends on 1)

The method of claim 1, wherein the bevel etch does not extend a depth of the trench.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
forming a gate dielectric lining the sidewall of the trench;
forming a gate electrode in the trench;
forming a well region in the semiconductor region; and
forming a source region in the well region adjacent the trench, the source region having a conductivity type opposite a conductivity type of the well region.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
forming a shield dielectric lining a lower portion of the sidewall and a bottom surface of the trench;
forming a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the shield dielectric;
forming an inter-electrode dielectric over the shield electrode;
forming a gate electrode in the trench over the inter-electrode dielectric;
forming a well region in the semiconductor region; and
forming a source region in the well region adjacent the trench, the source region having a conductivity type opposite a conductivity type of the well region.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
disposing, within the trench, a silicon material having a conductivity type opposite a conductivity type of the semiconductor region so that the silicon material and the semiconductor region collectively form at least a portion of a p-n pillar.

### Claim 15 (depends on 1)

The method of claim 1, wherein the semiconductor region includes an epitaxial layer extending over a substrate, and the trench is formed in the epitaxial layer, the method further comprising:
disposing within the trench a silicon material having a conductivity type opposite a conductivity type of the epitaxial layer such that the silicon material and the epitaxial layer form at least a portion of a p-n pillar.

### Claim 16

A method for forming a semiconductor structure, comprising:
forming a single masking layer over a semiconductor region;
forming an opening in the single masking layer;
performing a first etch to form a trench in the semiconductor region through the opening in the masking layer, the trench having a sidewall having a first slope, the trench defining a mesa region adjacent the trench;
removing completely the single masking layer; and
performing a second etch to taper the sidewall of the trench such that the sidewall of the trench has a second slope that is less than the first slope, and such that the trench has a width that gradually decreases from a top portion of the trench toward a bottom portion of the trench.

### Claim 17 (depends on 16)

The method of claim 16, wherein the trench is a first trench, the method further comprising:
forming a second trench, the mesa region being disposed between the first trench and the second trench, the second etch removing a layer of the semiconductor region along a top surface of the mesa region.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming the trench is performed using a plasma dry etch.

### Claim 19 (depends on 16)

The method of claim 16, wherein the second etch is performed using at least one fluorine-containing gas and at least one inert gas.

### Claim 20 (depends on 16)

The method of claim 16, wherein an angle θ of a profile of the trench is provided by:
tan
⁢
⁢
θ
=
1
t
·
C
·
Φ
⁡
(
0
)
·
1
S
⁡
(
L
+
S
)
,
wherein t represents etch time, C is an etch rate constant, and Φ(0) represents flux of an etchant species at a trench depth “0”.

### Claim 21 (depends on 16)

The method of claim 16, further comprising:
forming a gate dielectric lining the sidewall of the trench;
forming a gate electrode in the trench;
forming a well region in the semiconductor region; and
forming a source region in the well region adjacent the trench, the source region having a conductivity type opposite a conductivity type of the well region.

### Claim 22 (depends on 16)

The method of claim 16, further comprising:
forming a shield dielectric lining a lower portion of the sidewall and a bottom surface of the trench;
forming a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the shield dielectric;
forming an inter-electrode dielectric over the shield electrode;
forming a gate electrode in the trench over the inter-electrode dielectric;
forming a well region in the semiconductor region; and
forming a source region in the well region adjacent the trench, the source region having a conductivity type opposite a conductivity type of the well region.

### Claim 23 (depends on 16)

The method of claim 16, further comprising:
disposing within the trench a silicon material having a conductivity type opposite a conductivity type of the semiconductor region such that the silicon material and the semiconductor region collectively form at least a portion of a p-n pillar.

### Claim 24 (depends on 16)

The method of claim 16, wherein the semiconductor region includes an epitaxial layer extending over a substrate, and the trench is formed in the epitaxial layer, the method further comprising:
disposing within the trench a silicon material having a conductivity type opposite a conductivity type of the epitaxial layer such that the silicon material and the epitaxial layer form at least a portion of a p-n pillar.

### Claim 25 (depends on 1)

The method of claim 1, wherein the second slope is substantially constant from a top of the trench to a bottom of the trench.

### Claim 26 (depends on 1)

The method of claim 1, wherein the bevel etch removes a layer of the semiconductor region in the mesa region.

### Claim 27

A method for forming a semiconductor structure, comprising:
forming a single masking layer on a semiconductor region;
forming a trench in the semiconductor region using an opening in the single masking layer, the trench having a sidewall having a substantially constant first slope along a depth of the trench and defining a mesa region adjacent to the trench;
removing completely the single masking layer; and
tapering the sidewall of the trench so that the sidewall has a substantially constant second slope along the depth of the trench, the second slope being less than the first slope.

### Claim 28 (depends on 27)

The method of claim 27, further comprising, in conjunction with the tapering the sidewall, removing a layer of the semiconductor region in the mesa region.

### Claim 29 (depends on 27)

The method of claim 27, wherein the trench is a first trench and the opening is a first opening, the method further comprising:
forming a second trench in the semiconductor region using a second opening in the single masking layer, the mesa region being disposed between the first trench and the second trench.

### Claim 30 (depends on 27)

The method of claim 27, wherein:
the tapering the sidewall does not widen a width along a bottom of the trench; and
the tapering the sidewall does not extend a depth of the trench.