# US 8,772,168 B2 · Formation of the dielectric cap layer for a replacement gate structure

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- Number: US 8,772,168 B2
- Document ID: US8772168B2
- Status: Granted
- Kind: B2
- Application number: 13/353,708
- Filed: 2012-01-19
- Published: 2013-07-25
- Granted: 2014-07-08
- Earliest claimed: 2012-01-19
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: Ruilong Xie; Balasubramanian Pranatharthi Haran; David V. Horak; Su Chen Fan
- Inventors: Ruilong Xie; Balasubramanian Pranatharthi Haran; David V. Horak; Su Chen Fan
- Web page: https://patentgrep.com/patent/US8772168B2

## CPC

- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.

## Claims

### Claim 1

A method comprising:
forming a replaced gate structure on a substrate, the replaced gate structure comprising:
an interlayer dielectric (ILD) having a cavity,
a first metal on a top surface of the ILD and lining the cavity, and
a second metal on the first metal and filling the cavity;
planarizing the first and second metals down to the ILD;
forming an oxide on the second metal;
removing the oxide by a first etching;
forming a recess by recessing the first and second metals in the cavity by a second etching; and
filling the recess with a dielectric material.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the first metal comprises TiN, the second metal comprises aluminum (Al); and
the oxide comprises aluminum oxide (Al2O3).

### Claim 3 (depends on 1)

The method according to claim 1, comprising recessing the first and second metals to a depth of greater than 10 nm but less than or equal to 35 nm.

### Claim 4 (depends on 2)

The method according to claim 2, comprising:
planarizing the first and second metals down to the first metal; and
removing the first metal from the top surface of the ILD prior to filling the recess with a dielectric material.

### Claim 5 (depends on 4)

The method according to claim 4, comprising:
recessing the first and second metals by:
etching the second metal to a depth of 10 nm to 40 nm below the top surface of the ILD, and
etching the first metal to the same depth as the second metal; and
removing the first metal from the top surface of the ILD concurrently with etching the first metal.

### Claim 6 (depends on 4)

The method according to claim 4, comprising forming the replaced gate structure by depositing the first metal on the ILD and in the cavity by physical vapor deposition, to a thickness of 1 nm to 10 nm.

### Claim 7 (depends on 6)

The method according to claim 6, comprising:
planarizing the first and second metals down to the first metal; and
recessing the first and second metals by: thinning the first metal on the top surface of the ILD concurrently with etching the first and second metals.