# US 8,772,167 B2 · Method of forming a semiconductor memory device

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- Number: US 8,772,167 B2
- Document ID: US8772167B2
- Status: Granted
- Kind: B2
- Application number: 13/587,996
- Filed: 2012-08-17
- Published: 2013-04-18
- Granted: 2014-07-08
- Earliest claimed: 2011-10-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: JungWoo Seo; Kyoung Ryul Yoon; Kukhan Yoon
- Inventors: JungWoo Seo; Kyoung Ryul Yoon; Kukhan Yoon
- Web page: https://patentgrep.com/patent/US8772167B2

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 12/033: {the capacitor extending over the transistor}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10D 89/10: Integrated device layouts
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a semiconductor memory device includes forming an etch target layer on a substrate, forming a sacrificial layer having preliminary openings on the etch target layer, forming assistance spacers in the preliminary openings, respectively, removing the sacrificial layer, such that the assistance spacers remain on the etch target layer, forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings, forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction, and etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer.

## Claims

### Claim 1

A method of forming a semiconductor memory device, comprising:
forming an etch target layer on a substrate;
forming a sacrificial layer having preliminary openings on the etch target layer;
forming assistance spacers in the preliminary openings, respectively;
removing the sacrificial layer, such that the assistance spacers remain on the etch target layer;
forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings;
forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction; and
etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein defining the first openings includes forming the first openings two-dimensionally along rows and columns when viewed from a plan view, such that the rows are along a second direction and the columns are along a third direction crossing the second direction, and the first direction is non-parallel and non-perpendicular to the second and third directions.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein forming the first mask spacers and forming the second mask spacer is simultaneous.

### Claim 4 (depends on 3)

The method as claimed in claim 3, wherein forming the first mask spacers and the second mask spacer includes:
forming a mask spacer layer on the etch target layer and the assistance spacers; and
etching the mask spacer layer until a top surface of the etch target layer is exposed.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein forming the mask spacer layer includes depositing the mask spacer layer to a deposition thickness greater than a half of the shortest distance between a pair of the assistance spacers adjacent to each other in the second direction and a half of the shortest distance between a pair of the assistance spacers adjacent to each other in the third direction.

### Claim 6 (depends on 2)

The method as claimed in claim 2, wherein forming the second mask spacer includes filling with the second mask spacer a part of a space between the assistance spacers adjacent to each other in the second direction and a part of a space between the assistance spacers adjacent to each other in the third direction.

### Claim 7 (depends on 2)

The method as claimed in claim 2, wherein:
a distance between center points of two holes adjacent to each other in the first direction is represented as R3,
a distance between center points of two holes adjacent to each other in the second direction is represented as R2,
a distance between center points of two holes adjacent to each other in the third direction is represented as R1, and
R3 is represented by the following formula: R3=((R12+R22)/4)1/2.

### Claim 8 (depends on 7)

The method as claimed in claim 7, wherein the R1 is equal to the R2, and R3 is represented by the following formula: R3=R1/(21/2).

### Claim 9 (depends on 1)

The method as claimed in claim 1, further c v preliminary openings to enlarge the preliminary openings.

### Claim 10 (depends on 1)

The method as claimed in claim 1, wherein forming the sacrificial layer includes using a material having an etch selectivity with respect to the etch target layer and the assistance spacers.

### Claim 11

A method of forming a semiconductor memory device, comprising:
forming an etch target layer on a substrate;
forming a plurality of assistance spacers on the etch target layer, the assistance spacers being spaced apart from each other, and each of the assistance spacers defining an inner space exposing the etch target layer and an outer space exposing the etch target layer between the assistance spacers adjacent to each other;
forming a mask spacer layer on the etch target layer to fill a part of the inner space and a part of the outer space;
anisotropically etching the mask spacer layer until the etch target layer is exposed, such that openings exposing the etch target layer are formed, the openings including first openings exposing the etch target layer in the inner space and second openings exposing the etch target layer in the outer space; and
forming holes by etching the etch target layer exposed through the openings.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein forming the mask spacer layer includes depositing the mask spacer layer to a thickness that is greater than a half of the shortest distance between adjacent assistance spacers.

### Claim 13 (depends on 11)

The method as claimed in claim 11, wherein forming the openings includes arranging the openings two-dimensionally in rows along a first direction and in columns along a second direction when viewed from a plan view, the second direction being perpendicular to the first direction,
wherein center points of the openings arranged in two adjacent rows are misaligned in the second direction, and
wherein center points of the openings arranged in two adjacent columns are misaligned in the first direction.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein forming the openings includes:
forming the first openings in a first column of the two adjacent columns by etching through the defined inner spaces of the assistance spacers; and
forming the second openings in a second column of the two adjacent columns by etching through the defined outer spaces between the assistance spacers.

### Claim 15

A method of forming a semiconductor memory device, comprising:
forming an etch target layer on a substrate;
forming a plurality of assistance spacers on the etch target layer;
forming first mask spacers on inner sidewalls of the assistance spacers, the first mask spacers defining first openings in centers of the assistance spacers;
forming a second mask spacer on outer sidewalls of the assistance spacers, the second mask spacer defining second openings, each second opening being between two adjacent first openings along a first direction; and
etching the etch target layer through the first and second openings to form holes in the etch target layer.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein:
forming the plurality of assistance spacers includes forming a two dimensional matrix of assistance spacers, each spacer defining an inner space therein, and
forming the second openings along the first direction includes forming the second openings along a diagonal direction of the matrix.

### Claim 17 (depends on 15)

The method as claimed in claim 15, wherein:
forming the first mask spacers includes defining a size of the assistance spacers by a minimal distance of a lithography equipment, such that the first openings in respective centers of the assistance spacers are formed at the minimal distance of the lithography equipment; and
forming the second mask spacer includes forming the assistance spacers with small distances therebetween, such that a deposition thickness of a mask spacer layer is greater than a half of the shortest distance between a pair of the assistance spacers in a second or third direction, the second and third directions being perpendicular to each other.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein forming the assistance spacers includes:
forming preliminary openings through a sacrificial layer, centers of the preliminary openings being defined by the minimal distance of the lithography equipment;
etching the preliminary openings to expand diameters thereof, such that distances between the expanded preliminary openings along the second and third directions are reduced;
coating inner sidewalls of the preliminary openings; and
removing the sacrificial layer, such that the coating on the inner sidewalls of the preliminary openings defines the assistance spacers.

### Claim 19 (depends on 15)

The method as claimed in claim 15, wherein forming the holes includes forming a matrix with a plurality of first and second columns, the first and second columns being arranged to alternate and be offset with respect to each other.

### Claim 20 (depends on 19)

The method as claimed in claim 19, wherein forming the holes includes forming the first columns to include the first openings and the second columns to include the second openings, centers of the first openings being misaligned with respect to centers of the second openings.