# US 8,772,166 B2 · Spacer process for on pitch contacts and related structures

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- Number: US 8,772,166 B2
- Document ID: US8772166B2
- Status: Granted
- Kind: B2
- Application number: 13/526,792
- Filed: 2012-06-19
- Published: 2012-10-11
- Granted: 2014-07-08
- Earliest claimed: 2007-11-01
- Assignees: Micron Technology, Inc.
- Applicants: Gurtej Sandhu; Mark Kiehlbauch; Steve Kramer; John Smythe
- Inventors: Gurtej Sandhu; Mark Kiehlbauch; Steve Kramer; John Smythe
- Web page: https://patentgrep.com/patent/US8772166B2

## CPC

- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/43: Layouts of interconnections
- Y10S 438/942: Masking
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

## Claims

### Claim 1

A method for semiconductor processing, comprising:
providing a substrate;
providing a layer of selectively definable material over the substrate;
patterning the layer of selectively definable material to form a row of pillars and a block each formed of the selectively definable material, the block extending along a side of and contacting each of the pillars of the row of pillars, as seen in a top down view, the pillars having a linear density Z; and
replacing the row of pillars with a row of holes formed in a masking layer disposed on the level formerly occupied by the pillars, at least some of the holes disposed at locations formerly occupied by at least some of the pillars, the holes having a linear density greater than Z.

### Claim 2 (depends on 1)

The method of claim 1, wherein the block is disposed on one side of the row, and wherein patterning the selectively definable layer forms another block of selectively definable material on an opposite side of the row.

### Claim 3 (depends on 1)

The method of claim 1, wherein the pillars are symmetrical, as seen in a top down view.

### Claim 4 (depends on 1)

The method of claim 1, wherein the holes are symmetrical, as seen in a top down view.

### Claim 5 (depends on 1)

The method of claim 1, further comprising trimming the pillars and the block to separate the pillars and the block before replacing the row of pillars with the row of holes.

### Claim 6 (depends on 5)

The method of claim 5, further comprising selectively removing the block after replacing the row of pillars.

### Claim 7 (depends on 1)

The method of claim 1, wherein replacing the row of pillars with the row of holes comprises:
blanket depositing spacer material on the pillars;
anisotropically etching the spacer material to form spacers on sides of the pillars; and
selectively removing the pillars.

### Claim 8 (depends on 1)

The method of claim 1, wherein the linear density of the holes is about 1.5 times Z or more.

### Claim 9

A method for semiconductor processing, comprising:
providing a row of pillars and a block of selectively definable material extending along a side of the row of pillars, wherein the block and the pillars are in contact and extend on a same level over a substrate, as seen in a top down view, the pillars having a linear density Z;
replacing the row of pillars with a mask having a row of holes, the mask and holes disposed on the level, the holes having a width of about 60 nm or less, at least some of the holes disposed at a location formerly occupied by a pillar, wherein the holes have a linear density at least about 1.5 times Z; and
transferring a pattern defined by the holes to the substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein providing the row of pillars and the block comprises simultaneously forming the pillars and the block.

### Claim 11 (depends on 10)

The method of claim 10, wherein simultaneously forming the pillars and the block comprises patterning a selectively definable layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein patterning the selectively definable layer comprises patterning a photoresist layer to define the pillars and the block in the photoresist layer.

### Claim 13 (depends on 9)

The method of claim 9, wherein the linear density of the holes is about 2 times Z.

### Claim 14 (depends on 9)

The method of claim 9, wherein the holes have a width of about 30 nm or less.

### Claim 15 (depends on 9)

The method of claim 9, further comprising separating the block and the pillars by subjecting the block and the pillars to an etch.

### Claim 16 (depends on 9)

The method of claim 9, further comprising removing the block before transferring the pattern defined by the holes to the substrate.

### Claim 17 (depends on 9)

The method of claim 9, further comprising transferring a mask pattern formed by the mask having the row of holes to the substrate to form a row of contact vias in the substrate.

### Claim 18

A method for semiconductor processing, comprising:
providing a row of pillars and a block of masking material extending continuously along a length of the row of pillars, as seen in a top down view, the pillars having a linear density Z, the block spanning between a plurality of the pillars;
replacing the row of pillars with a mask having a row of holes, the mask and holes disposed on the level, the holes having a width of about 60 nm or less, at least some of the holes disposed at a location formerly occupied by a pillar, wherein the holes have a linear density at least about 1.5 times Z; and
transferring a pattern defined by the holes to the substrate.

### Claim 19 (depends on 18)

The method of claim 18, wherein the pillars and the block are formed of the same material.

### Claim 20 (depends on 18)

The method of claim 18, wherein providing the row of pillars and the block of masking material comprises simultaneously forming the row of pillars and the block of masking material.