# US 8,772,165 B2 · Methods of manufacturing gates for preventing shorts between the gates and self-aligned contacts and semiconductor devices having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,165 B2 - Document ID: US8772165B2 - Status: Granted - Kind: B2 - Application number: 13/182,614 - Filed: 2011-07-14 - Published: 2013-01-17 - Granted: 2014-07-08 - Earliest claimed: 2011-07-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Ju Youn Kim; Jedon Kim - Inventors: Ju Youn Kim; Jedon Kim - Web page: https://patentgrep.com/patent/US8772165B2 ## CPC - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/0112: {using conductive layers comprising silicides} - H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN} - H10D 84/014: {the gate conductors having different materials or different implants} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/817: {Combinations of field-effect devices and resistors only} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10D 30/0212: {using self-aligned silicidation} - H10D 64/685: {being perpendicular to the channel plane} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor device, comprising forming a metal gate of a transistor on a substrate by a replacement metal gate process, wherein an insulating layer is formed on the substrate adjacent the metal gate, forming a hard mask on the substrate including the insulating layer and the metal gate, the hard mask including an opening exposing the metal gate, performing a metal pull back process on the substrate to remove a predetermined depth of a top portion of the metal gate, depositing a protective layer on the substrate, including on the hard mask and on top of a remaining portion of the metal gate, and performing chemical mechanical polishing to remove the hard mask and the protective layer, wherein the protective layer formed on top of the remaining portion of the metal gate remains. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, comprising: forming a metal gate of a transistor on a substrate by a replacement metal gate process, wherein an insulating layer is formed on the substrate adjacent the metal gate; forming a hard mask on the substrate including the insulating layer and the metal gate, the hard mask including an opening exposing the metal gate; performing a metal pull back process on the substrate to remove a predetermined depth of a top portion of the metal gate; depositing a protective layer on the substrate, the hard mask and top of a remaining portion of the metal gate; and performing chemical mechanical polishing to remove the hard mask and the protective layer, wherein the protective layer formed on top of the remaining portion of the metal gate remains. ### Claim 2 (depends on 1) The method for manufacturing the semiconductor device according to claim 1, wherein the predetermined depth is approximately 100 angstroms. ### Claim 3 (depends on 1) The method for manufacturing the semiconductor device according to claim 1, wherein the protective layer includes silicon nitride. ### Claim 4 (depends on 1) The method for manufacturing the semiconductor device according to claim 1, further comprising removing the insulating layer. ### Claim 5 (depends on 1) The method for manufacturing the semiconductor device according to claim 1, wherein a chemical mechanical polishing process is performed on the insulating layer and the metal gate prior to forming the hard mask. ### Claim 6 (depends on 1) The method for manufacturing the semiconductor device according to claim 1, wherein the metal gate includes an outer layer comprising a different metal than that of an inner layer, the protective layer covering each of the inner and outer layers. ### Claim 7 (depends on 1) A computer system comprising a semiconductor device having a circuit layout manufactured by the method of claim 1, wherein the computer system is one of a personal computer (PC), a personal digital assistant (PDA), an MP3 player, a digital audio recorder, a pen-shaped computer, a digital camera, or a video recorder. ### Claim 8 (depends on 1) A system for transmitting or receiving data, the system comprising: a memory device for storing a program; and a processor in communication with the memory device, wherein the memory device comprises a circuit layout manufactured by the method of claim 1. ### Claim 9 (depends on 1) A semiconductor memory card, comprising: an interface part that interfaces with an external device; a controller that communicates with the interface part and a memory device via address and data buses, wherein the memory device comprises a circuit layout manufactured by the method of claim 1. ### Claim 10 (depends on 4) The method for manufacturing the semiconductor device according to claim 4, further comprising depositing a first dielectric layer on exposed portions of the substrate, including the protective layer formed on top of the remaining portion of the metal gate. ### Claim 11 (depends on 10) The method for manufacturing the semiconductor device according to claim 10, further comprising: depositing a second dielectric layer on the structure including the first dielectric layer; performing an open mask process to remove the first and second dielectric layers from areas adjacent the metal gate; and forming a silicide layer on portions of the substrate where the first and second dielectric layers were removed. ### Claim 12 (depends on 11) The method for manufacturing the semiconductor device according to claim 11, further comprising: depositing a third dielectric layer on the metal gate and on the silicide layer; etching the third dielectric layer disposed over the silicide layer to form a via; and filling the via with a metal to form an interconnect, wherein a portion of the metal fills vacant area on the protective layer, disposing the protective layer between the metal gate and the metal in the via, the protective layer blocking the metal in the via from contacting the metal gate. ### Claim 13 (depends on 12) The method for manufacturing the semiconductor device according to claim 12, wherein the metal filling the via comprises tungsten. ### Claim 14 (depends on 12) The method for manufacturing the semiconductor device according to claim 12, wherein the third dielectric layer comprises at least one of tetraethoxysilane (TEOS) and undoped silicate glass (USG). ### Claim 15 (depends on 8) The system according to claim 8, wherein the system comprises at least one of a mobile system, a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card. ### Claim 16 A method for manufacturing a semiconductor device, comprising; forming a metal gate of a transistor on a substrate by a replacement metal gate process, wherein an insulating layer is formed on the substrate adjacent the metal gate; depositing a protective layer on the substrate covering the insulating layer and a top surface of the metal gate; patterning the protective layer to remove the protective layer from the insulating layer adjacent the metal gate, wherein the protective layer remains covering the top surface of the metal gate; removing the insulating layer to expose the substrate adjacent the metal gate; and after removing the insulating layer, depositing a first dielectric layer on the exposed substrate and the protective layer covering the top surface of the metal gate. ### Claim 17 (depends on 16) The method for manufacturing the semiconductor device according to claim 16, wherein a thickness of the protective layer is about 50 angstroms to about 100 angstroms. ### Claim 18 (depends on 16) The method for manufacturing the semiconductor device according to claim 16, wherein the protective layer includes silicon nitride. ### Claim 19 (depends on 16) The method for manufacturing the semiconductor device according to claim 16, further comprising: depositing a second dielectric layer on the structure including the first dielectric layer; performing an open mask process to remove the first and second dielectric layers from areas adjacent the metal gate; and forming a silicide layer on portions of the substrate where the first and second dielectric layers were removed. ### Claim 20 (depends on 16) The method for manufacturing the semiconductor device according to claim 16, wherein a chemical mechanical polishing process is performed on the insulating layer and the metal gate prior to depositing the protective layer. ### Claim 21 (depends on 16) The method for manufacturing the semiconductor device according to claim 16, wherein the metal gate includes an outer layer comprising a different metal than that of an inner layer, the protective layer covering each of the inner and outer layers. ### Claim 22 (depends on 19) The method for manufacturing the semiconductor device according to claim 19, further comprising: depositing a third dielectric layer on the metal gate and on the silicide layer; etching the third dielectric layer disposed over the silicide layer to form a via; and filling the via with a metal to form an interconnect, wherein a portion of the metal fills a vacant area on the protective layer, disposing the protective layer between the metal gate and the metal in the via, the protective layer blocking the metal in the via from contacting the metal gate. ### Claim 23 (depends on 22) The method for manufacturing the semiconductor device according to claim 22, wherein the metal filling the via comprises tungsten. ### Claim 24 (depends on 22) The method for manufacturing the semiconductor device according to claim 22, wherein the third dielectric layer comprises at least one of tetraethoxysilane (TEOS) and undoped silicate glass (USG).