# US 8,772,157 B2 · Method of forming Cu interconnects

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- Number: US 8,772,157 B2
- Document ID: US8772157B2
- Status: Granted
- Kind: B2
- Application number: 13/667,492
- Filed: 2012-11-02
- Published: 2014-05-08
- Granted: 2014-07-08
- Earliest claimed: 2012-11-02
- Assignees: Shanghai Huali Microelectronics Corporation
- Applicants: Jingxun Fang
- Inventors: Jingxun Fang
- Web page: https://patentgrep.com/patent/US8772157B2

## CPC

- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10P 52/403: {of conductive or resistive materials}
- H10P 95/04: {Planarisation of conductive or resistive materials}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a method of forming Cu interconnects. The method comprises depositing an etch stop layer and an insulating layer subsequently; forming vias and trenches in the insulating layer; depositing a diffusion barrier layer and a copper seed layer using PVD; applying electroplating process to form the copper interconnects; depositing a layer of filling materials and reflowing the filling materials to eliminate the uneven surface topography of the copper interconnection layer; and applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing. According to the method of forming Cu interconnects, the uneven surface topography after electroplating can be reduced, and the surface topography after CMP can be planarized.

## Claims

### Claim 1

A method of forming Cu interconnects comprising:
Step 1: depositing an etch stop layer;
Step 2: depositing an insulating layer with certain thickness on the etch stop layer;
Step 3: applying photolithography and etching process to the insulating layer to form vias and trenches in the insulating layer;
Step 4: depositing a diffusion barrier layer and depositing a copper seed layer on the diffusion barrier layer using PVD;
Step 5: applying electroplating process to the top surface of the copper seed layer to form the copper interconnects;
Step 6, depositing a layer of filling materials adhering to copper and then reflowing the filling materials to eliminate the uneven surface topography of the copper interconnects, wherein the step 6 of applying CMP process further comprised:
Step 61, removing all the filling materials and parts of the copper interconnects on the diffusion barrier layer with the same removal rate;
Step 62, removing all the copper interconnects on the to surface of the insulating layer with high selectivity ratio of copper to the diffusion barrier layer, and stopping on the diffusion barrier layer; and
Step 63, removing the entire diffusion barrier layer on the to surface of the insulating layer; And
Step 7, applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing.

### Claim 2 (depends on 1)

The method according to claim 1, wherein, the filling materials are chosen from one of the metal alloy materials, macromolecule polymer materials, or compound materials of metal alloy and macromolecule polymer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein, the melting point of the filling materials is in the range from 100 degree Celsius to 900 degree Celsius.

### Claim 4 (depends on 2)

The method according to claim 2, wherein, the metal alloy materials are composed of two or more metals including magnesium, aluminum, copper, zinc, indium, stannum, stibium, and plumbum, and accompanied by one or more trace impurity elements, wherein the trace impurity elements comprise sulfur or arsenic.

### Claim 5 (depends on 4)

The method according to claim 4, wherein, the macromolecule polymer is a polymer or co-polymer formed by addition or condensation polymerization of one or more monomers.

### Claim 6 (depends on 1)

The method according to claim 1, wherein, the reflowing process is performed by heating and spinning to fill the recessed surface topography of the copper interconnects with the filling materials deposited on the copper interconnects.

### Claim 7 (depends on 1)

The method according to claim 1, wherein, the material of the diffusion barrier layer is Ta/TaN or Ru.

### Claim 8 (depends on 1)

The method according to claim 1, wherein, the material of the insulating layer is silicon oxide or low-k dielectric substance.

### Claim 9 (depends on 1)

The method according to claim 1, wherein, the material of the etch stop layer is SiC, SiCN or SiN.