# US 8,772,151 B2 · Passivation scheme

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- Number: US 8,772,151 B2
- Document ID: US8772151B2
- Status: Granted
- Kind: B2
- Application number: 13/629,180
- Filed: 2012-09-27
- Published: 2014-03-27
- Granted: 2014-07-08
- Earliest claimed: 2012-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US8772151B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/097: {by thermally treating}
- H10W 20/44: Conductive materials thereof
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10P 95/08: {Planarisation of organic insulating materials}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a passivation layer over an electrically conductive pad. A stress buffer layer is formed over the passivation layer. An opening is formed through the stress buffer layer over the electrically conductive pad wherein the opening does not reach the electrically conductive pad. The stress buffer layer is cured. The opening is extended through the passivation layer to reach the electrically conductive pad after the curing.

## Claims

### Claim 1

A method, comprising:
forming a first passivation layer over an electrically conductive pad;
forming a second passivation layer over the first passivation layer;
forming a first opening through the second passivation layer over the electrically conductive pad, wherein the first opening does not reach the electrically conductive pad;
forming a stress buffer layer over the second passivation layer and in the first opening;
forming a second opening through the stress buffer layer over the electrically conductive pad, wherein the second opening does not reach the electrically conductive pad;
curing the stress buffer layer; and
extending the second opening through the first passivation layer to reach the electrically conductive pad after the curing.

### Claim 2 (depends on 1)

The method of claim 1, wherein extending the second opening is performed by self-aligned etching using the stress buffer layer as a mask.

### Claim 3 (depends on 1)

The method of claim 1, wherein curing is performed by a heat treatment of the stress buffer layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the electrically conductive pad comprises copper or copper alloy.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first passivation layer comprises SiN, SiON, SiO2, tetraethyl orthosilicate (TEOS), or any combination thereof.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first passivation layer is formed to have a thickness that ranges from 500 Å to 1500 Å.

### Claim 7 (depends on 1)

The method of claim 1, wherein the stress buffer layer comprises polymer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the stress buffer layer is formed to have a thickness that ranges from 5 μm to 20 μm.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second passivation layer comprises multiple layers.

### Claim 10 (depends on 1)

The method of claim 1, wherein the second passivation layer is formed to have a thickness that ranges from 4 kilo-Angstroms (KÅ) to 12 KÅ.

### Claim 11

A method, comprising:
forming a first passivation layer over an electrically conductive pad, wherein the electrically conductive pad comprises copper or copper alloy and the passivation layer has a thickness that ranges from 500 Å to 1500 Å;
forming a second passivation layer over the first passivation layer;
forming a first opening through the second passivation layer over the electrically conductive pad, wherein the first opening does not reach the electrically conductive pad;
forming a stress buffer layer comprising polymer over the second passivation layer and the first opening, wherein a bottom surface of the stress buffer layer directly adjoins the first passivation layer;
forming a second opening through the stress buffer layer over the electrically conductive pad wherein the second opening does not reach the electrically conductive pad;
curing the stress buffer layer; and
extending the second opening through the first passivation layer to reach the electrically conductive pad by self-aligned etching using the stress buffer layer as a mask after the curing.

### Claim 12 (depends on 11)

The method of claim 11, wherein the passivation layer comprises SiN, SiON, SiO2, tetraethyl orthosilicate (TEOS), or any combination thereof.

### Claim 13 (depends on 11)

The method of claim 11, wherein curing the stress buffer layer is performed by a heat treatment of the stress buffer layer.

### Claim 14

A method comprising:
forming a conductive pad over a first surface of a substrate;
forming a first passivation layer over the first surface of the substrate;
forming a second passivation layer over the first passivation layer;
forming a first opening through the second passivation layer to the first passivation layer;
forming a first stress buffer layer over the second passivation layer and in the first opening;
forming a second opening through the first stress buffer layer to the first passivation layer, a first portion of the first buffer layer being between a sidewall of the first opening and a sidewall of the second opening;
performing a treatment on the first stress buffer layer; and
after performing the treatment on the first stress buffer layer, extending the second opening through the first passivation layer to expose a portion of the conductive pad.

### Claim 15 (depends on 14)

The method of claim 14 further comprising:
forming a conductive interconnect in the second opening and along the first stress buffer layer, the conductive interconnect contacting the conductive pad in the second opening;
forming a conductive under bump layer on the conductive interconnect; and
forming a conductive bump on the conductive under bump layer.

### Claim 16 (depends on 15)

The method of claim 15 further comprising forming a second stress buffer layer over the conductive interconnect, the conductive under bump layer extending through the second stress buffer layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein performing the treatment on the first stress buffer layer comprises curing the first stress buffer layer by a heat treatment.

### Claim 18 (depends on 14)

The method of claim 14, wherein the first passivation layer comprises SiN, SiON, SiO2, tetraethyl orthosilicate (TEOS), or any combination thereof, and wherein the first stress buffer layer comprises a polymer.

### Claim 19 (depends on 1)

The method of claim 1, wherein the stress buffer layer directly adjoins the second passivation layer along a sidewall of the first opening.

### Claim 20 (depends on 14)

The method of claim 14, wherein the first portion of the first stress buffer layer has a bottom surface directly adjoining a top surface of the first passivation layer, and wherein a sidewall of the second passivation layer directly adjoins the first portion of the first stress buffer layer.