# US 8,772,148 B1 · Metal gate transistors and fabrication method thereof

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- Number: US 8,772,148 B1
- Document ID: US8772148B1
- Status: Granted
- Kind: B1
- Application number: 14/030,026
- Filed: 2013-09-18
- Granted: 2014-07-08
- Earliest claimed: 2013-05-21
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Xinpeng Wang; Qiyang He
- Web page: https://patentgrep.com/patent/US8772148B1

## CPC

- H10D 30/00: Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method is provided for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.

## Claims

### Claim 1

A method for fabricating a metal gate transistor, comprising:
providing a semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming at least one dummy gate on the dielectric layer;
forming a first sidewall spacer around the dummy gate;
forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask;
removing the dummy gate to form a trench; and
forming a metal gate in the trench,
wherein:
the sidewalls of the gate dielectric layer are vertical sidewalls and perpendicular to the semiconductor substrate.

### Claim 2 (depends on 1)

The method according to claim 1, before forming the dummy gate, further including:
forming a work function layer protruding from the dummy gate on the dielectric layer.

### Claim 3 (depends on 1)

The method according to claim 1, after forming the metal gate, further including:
forming a source region and a drain region in the semiconductor substrate at both sides of the first sidewall spacer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein forming the gate dielectric layer further includes:
etching a portion of the dielectric layer exposed by the first sidewall spacer and the dummy gate using the first sidewall spacer and the dummy gate as an etching mask.

### Claim 5 (depends on 1)

The method according to claim 1, wherein forming the first sidewall spacer further includes:
forming a second sidewall spacer around the dummy gate;
forming the first sidewall spacer around the second sidewall spacer and sidewalls of a work function layer.

### Claim 6 (depends on 1)

The method according to claim 1, after forming the dummy gate, further including:
forming a hard mask layer.

### Claim 7 (depends on 1)

The method according to claim 1, wherein forming the first sidewall spacer further includes:
forming a first sidewall spacer material layer on the dielectric layer and sidewalls and top of the dummy gate; and
performing an etch back process to remove the first sidewall spacer material layer on the dielectric layer and the top of the dummy gate.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
the dummy gate includes a first dummy gate and a second dummy gate.

### Claim 9 (depends on 1)

The method according to claim 1, wherein:
the first sidewall spacer is made of silicon oxide.

### Claim 10 (depends on 2)

The method according to claim 2, wherein forming the work function layer further includes:
forming a work function material layer; and
etching the work function material layer using the first sidewall spacer as an etching mask.

### Claim 11 (depends on 7)

The method according to claim 7, wherein:
the first sidewall spacer material layer is formed by an atomic layer deposition process; and
thickness of the first sidewall spacer material layer is in a range of approximately 1 Ř50 Å.

### Claim 12 (depends on 10)

The method according to claim 10, wherein:
the work function layer is made of TiN.

### Claim 13 (depends on 10)

The method according to claim 10, wherein:
the first sidewall spacer covers sidewalls of the work function layer.