# US 8,772,143 B2 · Field effect transistor devices with dopant free channels and back gates

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- Number: US 8,772,143 B2
- Document ID: US8772143B2
- Status: Granted
- Kind: B2
- Application number: 13/676,927
- Filed: 2012-11-14
- Published: 2014-05-15
- Granted: 2014-07-08
- Earliest claimed: 2012-11-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Ali Khakifirooz; Ghavam G. Shahidi
- Web page: https://patentgrep.com/patent/US8772143B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.

## Claims

### Claim 1

A method of forming a back gate transistor device, the method comprising:
forming an open isolation trench in a substrate;
forming sidewall spacers in the open isolation trench; and
using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants;
wherein the performing the doping operation further comprises forming a dopant source insulator material within the open isolation trench, performing an annealing operation so as to drive dopants from the dopant source insulator material into the substrate, and performing one of:
recessing a portion of the dopant source insulator material and replacing the same with an undoped insulator material prior to performing the annealing operation; or
completely removing the dopant source insulator material following the annealing operation.

### Claim 2 (depends on 1)

The method of claim 1, wherein the doped well region comprises a p-type region, and the dopant source insulator material comprises boron-doped oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein the doped well region comprises an n-type region, and the dopant source insulator material comprises one or more of arsenic-doped oxide and phosphorous-doped oxide.

### Claim 4 (depends on 1)

The method of claim 1, wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, a buried insulator (BOX) layer formed on the bulk substrate layer, and an active SOI layer formed on the buried insulator layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the SOI substrate comprises an extremely thin SOI (ETSOI) substrate, with the active SOI layer having a thickness of about 10 nanometers (nm) or less.

### Claim 6 (depends on 4)

The method of claim 4, wherein the open isolation trench is formed completely through the active SOI layer and the BOX layer, and into a portion of the bulk substrate layer such that the sidewall spacers prevent contamination of the active SOI layer and the BOX layer by the dopants.

### Claim 7

A method of forming a back gate transistor device, the method comprising:
forming a protective pad layer over a semiconductor-on-insulator (SOI) substrate, the SOI substrate having a bulk substrate layer, a buried insulator (BOX) layer formed on the bulk substrate layer, and an active SOI layer formed on the buried insulator layer;
forming an open isolation trench through the protective pad layer, the active SOI layer, the BOX layer, and into a portion of the bulk substrate layer;
forming sidewall spacers in the open isolation trench; and
using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench and the BOX layer, such that the doped well region serves as a back gate conductor, wherein the sidewall spacers prevent contamination of the BOX layer and the active SOI layer device by dopants;
wherein the performing the doping operation further comprises forming a dopant source insulator material within the open isolation trench, performing an annealing operation so as to drive dopants from the dopant source insulator material into the bulk substrate layer, and performing one of:
recessing a portion of the dopant source insulator material and replacing the same with an undoped insulator material prior to performing the annealing operation; or
completely removing the dopant source insulator material following the annealing operation.

### Claim 8 (depends on 7)

The method of claim 7, further comprising refilling the open isolation trench with an undoped insulator material.

### Claim 9 (depends on 7)

The method of claim 7, wherein the doped well region comprises a p-type region, and the dopant source insulator material comprises boron-doped oxide.

### Claim 10 (depends on 7)

The method of claim 7, wherein the doped well region comprises an n-type region, and the dopant source insulator material comprises one or more of arsenic-doped oxide and phosphorous-doped oxide.

### Claim 11 (depends on 7)

The method of claim 7, wherein the SOI substrate comprises an extremely thin SOI (ETSOI) substrate, with the active SOI layer having a thickness of about 10 nanometers (nm) or less.