# US 8,772,137 B2 · Semiconductor wafer with assisting dicing structure and dicing method thereof

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- Number: US 8,772,137 B2
- Document ID: US8772137B2
- Status: Granted
- Kind: B2
- Application number: 14/132,192
- Filed: 2013-12-18
- Published: 2014-04-17
- Granted: 2014-07-08
- Earliest claimed: 2007-05-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Shih-Hsun Hsu
- Web page: https://patentgrep.com/patent/US8772137B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- B28D 5/022: {by cutting with discs or wheels}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B28D: WORKING STONE OR STONE-LIKE MATERIALS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.

## Claims

### Claim 1

A method for dicing a semiconductor wafer, comprising:
providing a semiconductor wafer having a front surface and a rear surface, wherein the front surface of the semiconductor wafer comprises at least two device regions separated by at least one dicing lane;
forming a plurality of pre-dicing trenches in the rear surface of the semiconductor wafer and without passing therethrough and substantially aligned with the dicing lane, wherein the plurality of pre-dicing trenches are arranged in a line extending along an extending direction of the dicing lane and each pre-dicing trench has a width less than that of the dicing lane; and
sawing through the semiconductor wafer, such that the sawing cuts partially through the plurality of pre-dicing trenches.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein each pre-dicing trench has a width wider than a width of a dicing blade for sawing the semiconductor wafer.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein a plurality of pairs of pre-dicing trenches is formed in the rear surface of the substrate, arranged in a line extending along the extending direction of the dicing lane.

### Claim 4 (depends on 3)

The method as claimed in claim 3, wherein each pair of pre-dicing trenches has a space therebetween and the space is narrower than a width of a dicing blade for sawing the semiconductor wafer.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein each pre-dicing trench of the pair of the pre-dicing trenches has a width, and the sum of the space and the total width of the pair of the dicing trenches exceeds a width of a dicing blade for sawing the semiconductor wafer.

### Claim 6 (depends on 3)

The method as claimed in claim 3, wherein each pair of pre-dicing trenches is rectangular in a plan view.

### Claim 7 (depends on 6)

The method as claimed in claim 6, wherein each pair of pre-dicing trenches has a length edge parallel to the extending direction of the dicing lane.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein the sidewalls of the plurality of pre-dicing trench are tapered.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein the plurality of pre-dicing trenches is formed by sawing, etching, laser ablating, or ion milling.

### Claim 10 (depends on 1)

The method as claimed in claim 1, wherein each pre-dicing trench is square or circular.

### Claim 11 (depends on 1)

The method as claimed in claim 1, wherein the semiconductor wafer is sawed from the dicing lane of the front surface to the rear surface.

### Claim 12 (depends on 1)

The method as claimed in claim 1, wherein the semiconductor wafer is sawed from the rear surface substantially aligned with the dicing lane to the front surface.