# US 8,772,135 B2 · Semiconductor device manufacturing method using laser irradiation and dicing saw and semiconductor device thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,135 B2 - Document ID: US8772135B2 - Status: Granted - Kind: B2 - Application number: 13/310,170 - Filed: 2011-12-02 - Published: 2012-03-29 - Granted: 2014-07-08 - Earliest claimed: 2005-11-10 - Assignees: Renesas Electronics Corporation - Applicants: Yoshiyuki Abe; Chuichi Miyazaki; Hideo Mutou; Tomoko Higashino - Inventors: Yoshiyuki Abe; Chuichi Miyazaki; Hideo Mutou; Tomoko Higashino - Web page: https://patentgrep.com/patent/US8772135B2 ## CPC - B23K 26/0006: {taking account of the properties of the material involved (B23K26/32, B23K26/40 take precedence)} - B23K 26/40: taking account of the properties of the material involved - B23K 26/53: for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks - G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)} - H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) - H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/0428: {Apparatus for mechanical treatment or grinding or cutting} - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - H10P 72/78: using vacuum or suction, e.g. Bernoulli chucks - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 74/016: {using moulds} - H10W 90/00: Package configurations - B23K 2101/40: Semiconductor devices - B23K 2103/50: {Inorganic materials other than metals or composite materials} - B23K 2103/56: {being semiconducting} - H10P 72/7416: {used during dicing or grinding} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10W 46/101: {characterised by the type of information, e.g. logos or symbols} - H10W 46/301: {for alignment} - H10W 46/503: {Located in scribe lines} - H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/967: {Multiple bond pads having different functions} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/284: {characterised by structural arrangements for measuring or testing} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented. ## Claims ### Claim 1 A method of manufacturing a semiconductor device comprising the steps of: (a) providing a semiconductor wafer including a substrate having a front surface and a back surface opposite to the front surface, an interlayer insulating film formed on the front surface of the substrate, a cutting region located between a first chip region of the semiconductor wafer and a second chip region of the semiconductor wafer arranged next to the first chip region in a plan view, and a metal pattern formed over the front surface of the substrate and formed in the cutting region in the plan view, wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film, and wherein a dielectric constant of the low-dielectric constant film is lower than that of silicon oxide; (b) after the step of (a), forming a first modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and only between the first chip region and the metal pattern with a laser, and forming a second modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and only between the second chip region and the metal pattern with the laser, wherein only portions of the semiconductor wafer, which do not overlap with any metal layers including the metal pattern in the plan view, are irradiated with the laser, respectively; and (c) after the step of (b), removing the metal pattern, the interlayer insulating film and a portion of the substrate with a dicing saw along the cutting region and between the first modified region and the second modified region, wherein a width of the dicing saw is less than a distance between the first modified region and the second modified region. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein the low-dielectric constant film is comprised of one of an organic polymer, organic silica glass, complete-organic SiOF (fluorinated silicon oxide), HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), porous HSQ-based materials, porous MSQ-based materials and porous organic materials. ### Claim 3 (depends on 2) The method of manufacturing a semiconductor device according to claim 2, wherein, in the step (b), the first and second modified regions are formed into the substrate. ### Claim 4 (depends on 3) The method of manufacturing a semiconductor device according to claim 3, wherein, after the step (a), and before the step (b), a tape is attached over the front surface of the semiconductor wafer, and the back surface of the semiconductor wafer is ground; and wherein, after the step (b), and before the step (c), removing the tape from the semiconductor wafer. ### Claim 5 (depends on 4) The method of manufacturing a semiconductor device according to claim 4, wherein, after the step (c), the semiconductor wafer is bent. ### Claim 6 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is comprised of silicon. ### Claim 7 A method of manufacturing a semiconductor device comprising the steps of: (a) providing a semiconductor wafer including a substrate having a front surface and a back surface opposite to the front surface, an interlayer insulating film formed on the front surface of the substrate, a cutting region located between a first chip region of the semiconductor wafer and a second chip region of the semiconductor wafer arranged next to the first chip region in a plan view, and a metal pattern formed over the front surface of the substrate and formed in the cutting region in the plan view, wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film, wherein a dielectric constant of the low-dielectric constant film is lower than that of silicon oxide, and wherein the low-dielectric constant film is more brittle than the substrate; (b) after the step of (a), forming a first modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and between the first chip region and the metal pattern with a laser, and forming a second modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and between the second chip region and the metal pattern with the laser wherein only portions of the semiconductor wafer, which do not overlap with any metal layers including the metal pattern in the plan view, are irradiated with the laser, respectively; and (c) after the step of (b), removing the metal pattern, the interlayer insulating film and a portion of the substrate with a dicing saw along the cutting region and between the first modified region and the second modified region, wherein a width of the dicing saw is less than a distance between the first modified region and the second modified region. ### Claim 8 (depends on 7) The method of manufacturing a semiconductor device according to claim 7, wherein the low-dielectric constant film is comprised of one of an organic polymer, organic silica glass, complete-organic SiOF (fluorinated silicon oxide), HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), porous MSQ-based materials and porous organic materials. ### Claim 9 (depends on 8) The method of manufacturing a semiconductor device according to claim 8, wherein, in the step (b), the first and second modified regions are formed into the substrate. ### Claim 10 (depends on 9) The method of manufacturing a semiconductor device according to claim 9, wherein, after the step (a), and before the step (b), a tape is attached over the front surface of the semiconductor wafer, and the back surface of the semiconductor wafer is ground; and wherein after the step (b), and before the step (c), removing the tape from the semiconductor wafer. ### Claim 11 (depends on 10) The method of manufacturing a semiconductor device according to claim 10, wherein, after the step (c), the semiconductor wafer is bent. ### Claim 12 (depends on 11) The method of manufacturing a semiconductor device according to claim 11, wherein the substrate is comprised of silicon. ### Claim 13 A method of manufacturing a semiconductor device comprising the steps of: (a) providing a semiconductor wafer including a substrate having a front surface and a back surface opposite to the front surface, an interlayer insulating film formed on the front surface of the substrate, a cutting region located between a first chip region of the semiconductor wafer and a second chip region of the semiconductor wafer arranged next to the first chip region in a plan view, and a metal pattern formed over the front surface of the substrate and formed in the cutting region in the plan view, wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film, and wherein a dielectric constant of the low-dielectric constant film is lower than that of silicon oxide; (b) after the step of (a), forming a first modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and between the first chip region and the metal pattern with a laser, and forming a second modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and between the second chip region and the metal pattern with the laser, wherein only portions of the semiconductor wafer, which do not overlap with any metal layers including the metal pattern in the plan view, are irradiated with the laser, respectively; and (c) after the step of (b), removing the metal pattern, the interlayer insulating film and a portion of the substrate with a dicing saw along the cutting region and between the first modified region and the second modified region, wherein a width of the dicing saw is less than or equal to a distance between the first modified region and the second modified region. ### Claim 14 A method of manufacturing a semiconductor device comprising the steps of: (a) providing a semiconductor wafer including a substrate having a front surface and a back surface opposite to the front surface, an interlayer insulating film formed on the front surface of the substrate, a cutting region located between a first chip region of the semiconductor wafer and a second chip region of the semiconductor wafer arranged next to the first chip region in a plan view, and a metal pattern formed over the front surface of the substrate and formed in the cutting region in the plan view, wherein the interlayer insulating film has a wiring layer and a low-dielectric constant film, wherein a dielectric constant of the low-dielectric constant film is lower than that of silicon oxide, and wherein the low-dielectric constant film is more brittle than the substrate; (b) after the step of (a), forming a first modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and only between the first chip region and the metal pattern with a laser, and forming a second modified region in the cutting region of the semiconductor wafer by irradiating along the cutting region and only between the second chip region and the metal pattern with the laser, and wherein only portions of the semiconductor wafer, which do not overlap with any metal layers including the metal pattern in the plan view, are irradiated with the laser, respectively; and (c) after the step of (b), removing the metal pattern, the interlayer insulating film and a portion of the substrate with a dicing saw along the cutting region and between the first modified region and the second modified region, wherein a width of the dicing saw is less than or equal to a distance between the first modified region and the second modified region.