# US 8,772,127 B2 · Semiconductor device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,127 B2 - Document ID: US8772127B2 - Status: Granted - Kind: B2 - Application number: 13/142,591 - Filed: 2011-01-27 - Published: 2012-07-05 - Granted: 2014-07-08 - Earliest claimed: 2010-12-29 - Assignees: Institute of Microelectronics, Chinese Academy of Sciences - Applicants: Haizhou Yin; Huicai Zhong; Huilong Zhu; Zhijiong Luo - Inventors: Haizhou Yin; Huicai Zhong; Huilong Zhu; Zhijiong Luo - Web page: https://patentgrep.com/patent/US8772127B2 ## CPC - H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate} - H10D 30/795: {being in lateral device isolation regions, e.g. STI} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 62/405: {Orientations of crystalline planes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, comprising: providing a silicon substrate having {100} crystal indices with a gate stack structure formed thereon; forming a second isolation region within the silicon substrate wherein the second isolation region comprises a second dielectric layer; forming an interlayer dielectric layer to cover a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure above the second isolation region, and the second dielectric layer is exposed at a bottom of the first trench, wherein the first trench has an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile-stressed dielectric layer. ### Claim 2 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the first dielectric layer is a tensile-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride. ### Claim 3 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the first dielectric layer has a tensile stress of at least 1 GPa. ### Claim 4 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the gate stack structure comprises a gate electrode or a dummy gate electrode. ### Claim 5 (depends on 4) The method for manufacturing a semiconductor device of claim 4, wherein if the gate stack structure is a dummy gate electrode, the method further comprises: performing an annealing process after the first dielectric layer is formed in order to memorize the tensile stress provided by the first dielectric layer in the silicon substrate. ### Claim 6 (depends on 1) The method for manufacturing a semiconductor device of claim 1, further comprising: forming a third isolation region in the silicon substrate, wherein the third isolation region has an extension direction perpendicular to that of the second isolation region, and wherein a MOS transistor comprising the gate stack structure is formed on the area of the silicon substrate surrounded by the second isolation region and the third isolation region, the third isolation region comprises a third dielectric layer. ### Claim 7 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the second dielectric layer is a tensile-stressed dielectric layer. ### Claim 8 (depends on 7) The method for manufacturing a semiconductor device of claim 7, wherein the second dielectric layer is a tensile-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride. ### Claim 9 (depends on 7) The method for manufacturing a semiconductor device of claim 7, wherein the second dielectric layer has a tensile stress of at least 1 GPa. ### Claim 10 (depends on 6) The method for manufacturing a semiconductor device of claim 6, wherein the third dielectric layer is a low-stressed dielectric layer. ### Claim 11 (depends on 10) The method for manufacturing a semiconductor device of claim 10, wherein the third dielectric layer is a low-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride. ### Claim 12 (depends on 10) The method for manufacturing a semiconductor device of claim 10, wherein the third dielectric layer has a stress of not more than 180 MPa. ### Claim 13 (depends on 1) The method for manufacturing a semiconductor device of claim 1 further comprises a top surface of the second dielectric layer is lower than the top surface of the silicon substrate, and the first dielectric layer extends into the silicon substrate. ### Claim 14 (depends on 6) The method for manufacturing a semiconductor device of claim 6 further comprises a top surface of the third dielectric layer is lower than the top surface of the silicon substrate, and the first dielectric layer extends into the silicon substrate. ### Claim 15 (depends on 1) The method for manufacturing a semiconductor device of claim 1 further comprises the second isolation region has an extension direction along the <110> crystal direction and perpendicular to the extension direction of the gate stack structure. ### Claim 16 (depends on 6) The method for manufacturing a semiconductor device of claim 6 further comprises the second isolation region has an extension direction along the <110> crystal direction and perpendicular to the extension direction of the gate stack structure.