# US 8,772,125 B2 · Method of double-sided patterning

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- Number: US 8,772,125 B2
- Document ID: US8772125B2
- Status: Granted
- Kind: B2
- Application number: 13/712,059
- Filed: 2012-12-12
- Published: 2013-06-13
- Granted: 2014-07-08
- Earliest claimed: 2011-12-12
- Assignees: Shanghai Hua Hong NEC Electronics Co., Ltd.
- Applicants: Shanghai Hua Hong Nec Electronics Co., Ltd.
- Inventors: Lei Wang; Xiaobo Guo
- Web page: https://patentgrep.com/patent/US8772125B2

## CPC

- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 52/402: {of semiconductor materials}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P 72/7416: {used during dicing or grinding}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer.

## Claims

### Claim 1

A method of double-sided patterning, comprising, in the following order, the steps of:
positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches on the back side of the first silicon wafer, the one or more deep trenches serving as one or more deep trench alignment marks which can be used in subsequent lithographic processes consisting of front-side process and back-side process;
performing alignment with respect to the one or more deep trench alignment marks while forming a back-side device structure on the back side of the first silicon wafer;
depositing a polishing stop layer directly on a surface of the back side of the first silicon wafer;
flipping over the first silicon wafer so as to have its front side face upwards and bonding the back side of the first silicon wafer with a front side of a second silicon wafer;
polishing the front side of the first silicon wafer until a thickness of the first silicon wafer is reduced to a predetermined thickness such that the one or more deep trench alignment marks are exposed from the front side of the first silicon wafer;
performing alignment with respect to the one or more deep trench alignment marks while forming a front-side device structure on the front side of the first silicon wafer;
polishing a back side of the second silicon wafer until the polishing stop layer is reached; and
removing the polishing stop layer so as to obtain a double-sided patterned structure on the first silicon wafer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the one or more deep trenches have a depth greater than the predetermined thickness of the first silicon wafer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the one or more deep trenches are hollow.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the one or more deep trenches are filled with a non-metallic inorganic compound of silicon, oxygen, nitrogen or carbon.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the one or more deep trenches are filled with silicon nitride, silicon oxynitride or silicon dioxide.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the one or more deep trenches are filled with silicon dioxide.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the one or more deep trenches are filled with aluminum, copper or tungsten.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the polishing stop layer is formed of a compound of silicon, oxygen, nitrogen or carbon.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the polishing stop layer is formed of silicon nitride, silicon oxynitride or silicon dioxide.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the polishing stop layer is formed of silicon dioxide and has a thickness of 100 Å to 10 μm.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the polishing stop layer fully covers the topography of the back-side device structure on the back side of the first silicon wafer.