# US 8,772,119 B2 · Fabricating method of transistor

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- Number: US 8,772,119 B2
- Document ID: US8772119B2
- Status: Granted
- Kind: B2
- Application number: 13/236,656
- Filed: 2011-09-20
- Published: 2013-03-21
- Granted: 2014-07-08
- Earliest claimed: 2011-09-20
- Assignees: Nanya Technology Corporation
- Applicants: Kuo-Hui Su; Yi-Nan Chen; Hsien-Wen Liu
- Inventors: Kuo-Hui Su; Yi-Nan Chen; Hsien-Wen Liu
- Web page: https://patentgrep.com/patent/US8772119B2

## CPC

- H10D 30/0273: {forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/01308: {the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.

## Claims

### Claim 1

A fabricating method of a transistor, comprising:
forming a patterned sacrificed layer on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate;
by using the patterned sacrificed layer as a mask, performing a doping process on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings;
performing a selective growth process to form a source and a drain on the doped source region and the doped drain region, respectively;
removing the patterned sacrificed layer to expose the substrate between the source and the drain; and
forming a gate on the substrate between the source and the drain, wherein a height of the gate is substantially the same as a height of the source and the drain.

### Claim 2 (depends on 1)

The fabricating method as claimed in claim 1, wherein a height of the source and the drain is from 15 nm to 50 nm.

### Claim 3 (depends on 1)

The fabricating method as claimed in claim 1, wherein the selective growth process comprises a selective silicon growth process.

### Claim 4 (depends on 1)

The fabricating method as claimed in claim 1, wherein a material of the patterned sacrificed layer comprises silicon oxide.

### Claim 5 (depends on 1)

The fabricating method as claimed in claim 1, wherein a thickness of the patterned sacrificed layer is smaller than or equal to 10 nm.

### Claim 6 (depends on 1)

The fabricating method as claimed in claim 1, wherein a method of removing the patterned sacrificed layer comprises a stripping process.

### Claim 7 (depends on 1)

The fabricating method as claimed in claim 1, wherein the gate comprises a gate dielectric layer and a gate conductive layer which are sequentially formed on the substrate.

### Claim 8 (depends on 7)

The fabricating method as claimed in claim 7, wherein the gate conductive layer comprises a polysilicon layer and a silicide layer.

### Claim 9 (depends on 1)

The fabricating method as claimed in claim 1, wherein a method of forming the gate comprises:
forming a gate dielectric material layer on the substrate to cover the source and the drain;
forming a gate conductive material layer on the gate dielectric material layer; and
by using tops of the source and the drain as a polishing stop layer, performing a planarization process to the gate dielectric material layer and the gate conductive material layer.

### Claim 10 (depends on 9)

The fabricating method as claimed in claim 9, wherein the planarization process comprises a chemical mechanical polishing process.

### Claim 11 (depends on 9)

The fabricating method as claimed in claim 9, wherein the gate conductive material layer comprises a polysilicon material layer and a silicide material layer.

### Claim 12 (depends on 1)

The fabricating method as claimed in claim 1, further comprising forming an insulating layer on the substrate to cover the gate, the source, and the drain.

### Claim 13 (depends on 12)

The fabricating method as claimed in claim 12, further comprising forming a plurality of contacts in the insulating layer to electrically connect the source and the drain, respectively.

### Claim 14 (depends on 12)

The fabricating method as claimed in claim 12, wherein a material of the insulating layer comprises tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG).