# US 8,772,118 B2 · Offset screen for shallow source/drain extension implants, and processes and integrated circuits

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,118 B2
- Document ID: US8772118B2
- Status: Granted
- Kind: B2
- Application number: 13/484,592
- Filed: 2012-05-31
- Published: 2013-01-10
- Granted: 2014-07-08
- Earliest claimed: 2011-07-08
- Assignees: Texas Instruments Incorporated
- Applicants: Amitabh Jain
- Inventors: Amitabh Jain
- Web page: https://patentgrep.com/patent/US8772118B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

## Claims

### Claim 1

A process of integrated circuit manufacturing comprising:
providing a first gate stack and a second gate stack over a substrate;
forming a spacer on the sidewalls of the first gate stack and the second gate stack to provide a first horizontal offset over a first channel region under the first gate stack;
performing a PLDD implant adjacent the first gate stack having the first horizontal offset provided by said spacer;
after performing the PLDD implant, depositing a seal substance over the spacer, the first gate stack and the second gate stack to provide a screen thickness vertically while thereby augmenting the spacer on the second gate stack to provide a second, increased, offset horizontally from the second gate stack; and
subsequently providing an NLDD implant dose for NLDD formation using the unetched seal substance as a horizontal screen.

### Claim 2 (depends on 1)

The process claimed in claim 1 wherein the seal substance comprises at least one energy-reducing substance to reduce average energy of the NLDD implant dose entering the substrate to form n-type the source and drain extensions and thereby make the NLDD junction depth shallower.

### Claim 3 (depends on 1)

The process claimed in claim 1 wherein the seal substance includes silicon nitride (SiN).

### Claim 4 (depends on 1)

The process claimed in claim 1 wherein said step of forming a spacer comprises depositing a spacer material having a spacer thickness in a range about 40 A to 80 A.

### Claim 5 (depends on 4)

The process claimed in claim 4 wherein said steps of forming the spacer further includes anisotropic etching to diminish the spacer thickness to a range 30 A to 70 A prior to PLDD implant.

### Claim 6 (depends on 1)

The process claimed in claim 1 wherein said second horizontal offset is in a range of about 1.2 to 2 times a thickness of the seal vertically.

### Claim 7 (depends on 1)

The process claimed in claim 1 wherein said second horizontal offset is in a range about 1.5 to 2.5 times the first horizontal offset of the spacer prior to PLDD implant.

### Claim 8 (depends on 1)

The process claimed in claim 1 wherein the second horizontal offset is in a range of about 50 A to 120 A.