# US 8,772,117 B2 · Combination FinFET and planar FET semiconductor device and methods of making such a device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,117 B2 - Document ID: US8772117B2 - Status: Granted - Kind: B2 - Application number: 13/705,261 - Filed: 2012-12-05 - Published: 2014-06-05 - Granted: 2014-07-08 - Earliest claimed: 2012-12-05 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Inc. - Inventors: Min-hwa Chi; Werner Juengling - Web page: https://patentgrep.com/patent/US8772117B2 ## CPC - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/834: {comprising FinFETs} - H10D 86/011: {comprising FinFETs} - H10D 86/215: {comprising FinFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer. ## Claims ### Claim 1 A method of forming a device comprised of a plurality of fins and a plurality of trenches formed in a substantially un-doped layer of semiconducting material, the method comprising: identifying a top width of each of said plurality of fins and a depth of each of said plurality of trenches such that, during operation, said device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to said device; performing at least one process operation to define said plurality of trenches in said substantially un-doped layer of semiconducting material, wherein said trenches define said plurality of fins in said substantially un-doped layer of semiconducting material; forming a gate insulation layer on said plurality of fins and on a bottom surface of each of said trenches; and forming a gate electrode above said gate insulation layer. ### Claim 2 (depends on 1) The method of claim 1, wherein said bottom surface of said trenches defines a planar channel region for said device. ### Claim 3 (depends on 1) The method of claim 1, wherein performing said at least one process operation comprises performing an etching process. ### Claim 4 (depends on 1) The method of claim 1, wherein said substantially un-doped layer of semiconducting material is a layer of epitaxially deposited substantially un-doped silicon. ### Claim 5 (depends on 1) The method of claim 1, wherein said substantially un-doped layer of semiconducting material is an active layer of an SOI substrate. ### Claim 6 (depends on 1) The method of claim 1, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of semiconducting material. ### Claim 7 (depends on 1) The method of claim 1, wherein said gate insulation layer and said gate electrode fills said plurality of trenches. ### Claim 8 A method of forming a device comprised of a plurality of fins and a plurality of trenches formed in a substantially un-doped layer of semiconducting material, the method comprising: forming a buffer layer comprised of at least carbon in a substrate; performing an epitaxial deposition process to form a substantially un-doped layer of epitaxial silicon above said buffer layer; identifying a top width of each of said plurality of fins and a depth of each of said plurality of trenches such that, during operation, said device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to said device; performing at least one process operation to define said plurality of trenches in said substantially un-doped layer of semiconducting material, wherein said trenches define said plurality of fins in said substantially un-doped layer of epitaxial silicon; forming a gate insulation layer on said plurality of fins and on a bottom of each of said trenches; and forming a gate electrode above said gate insulation layer. ### Claim 9 (depends on 8) The method of claim 8, wherein performing said at least one process operation comprises performing an etching process. ### Claim 10 (depends on 8) The method of claim 8, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of epitaxial silicon. ### Claim 11 A method of forming a combination device in a substantially un-doped layer of semiconducting material, wherein said combination device is comprised of a plurality of spaced-apart FinFET device portions, each of which are comprised of at least one fin, and a plurality of substantially planar FET device portions, wherein the method comprises: identifying a target threshold voltage for said combination device; identifying at least one of a target top width of each of said fins or a target thickness of said substantially planar FET device portions such that, during operation, said combination device is intended to exhibit said target threshold voltage; forming a plurality of trenches in said substantially un-doped layer of semiconducting material so as to define said plurality of fins and said substantially planar FET device portions, wherein each of said fins have a top width that is approximately equal to said target top width, and said substantially planar FET device portions have a thickness that is approximately equal to said target thickness; forming a gate insulation layer on said plurality of fins and on an upper surface of said substantially planar FET device portions; and forming a gate electrode above said gate insulation layer. ### Claim 12 (depends on 11) The method of claim 11, wherein said target threshold voltage for said combination device comprises a target threshold voltage for said FinFET device portions that is greater than a target threshold voltage for said substantially planar FET device portions. ### Claim 13 (depends on 11) The method of claim 11, wherein said target threshold voltage for said combination device comprises a target threshold voltage for said FinFET device portions that is less than a target threshold voltage for said substantially planar FET device portions. ### Claim 14 (depends on 11) The method of claim 11, wherein said target threshold voltage for said combination device comprises a target threshold voltage for said FinFET device portions that is substantially equal to a target threshold voltage for said substantially planar FET device portions. ### Claim 15 (depends on 11) The method of claim 11, wherein said bottom surface of said trenches defines said upper surface of said substantially planar FET device portions. ### Claim 16 (depends on 11) The method of claim 11, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of semiconducting material. ### Claim 17 (depends on 11) The method of claim 11, wherein said gate insulation layer and said gate electrode fills said plurality of trenches. ### Claim 18 A method of forming a combination device in a substantially un-doped layer of semiconducting material, wherein said combination device is comprised of a plurality of spaced-apart FinFET device portions, each of which are comprised of at least one fin, and a plurality of substantially planar FET device portions, wherein the method comprises: identifying a target threshold voltage that is the same for said FinFET device portions and said substantially planar FET device portions; identifying a target top width of each of said fins such that, during operation, said FinFET device portions are intended to exhibit said target threshold voltage; identifying a target thickness of said substantially planar FET device portions such that, during operation, said planar FET portions are intended to exhibit said target threshold voltage; forming a plurality of trenches in said substantially un-doped layer of semiconducting material so as to define said plurality of fins and said substantially planar FET device portions, wherein each of said fins have a top width that is approximately equal to said target top width, and said substantially planar FET device portions have a thickness that is approximately equal to said target thickness; forming a gate insulation layer on said plurality of fins and on an upper surface of said substantially planar FET device portions; and forming a gate electrode above said gate insulation layer. ### Claim 19 (depends on 18) The method of claim 18, wherein said bottom surface of said trenches defines said upper surface of said substantially planar FET device portions. ### Claim 20 (depends on 18) The method of claim 18, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of semiconducting material. ### Claim 21 (depends on 18) The method of claim 18, wherein said gate insulation layer and said gate electrode fills said plurality of trenches.