# US 8,772,116 B2 · Dielectric equivalent thickness and capacitance scaling for semiconductor devices

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- Number: US 8,772,116 B2
- Document ID: US8772116B2
- Status: Granted
- Kind: B2
- Application number: 13/692,603
- Filed: 2012-12-03
- Published: 2014-05-22
- Granted: 2014-07-08
- Earliest claimed: 2012-11-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alessandro Callegari; Ko-Tao Lee; Devendra K. Sadana; Kuen-Ting Shiu
- Web page: https://patentgrep.com/patent/US8772116B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.

## Claims

### Claim 1

A device, comprising:
semiconductor material; and
a capacitor dielectric formed over the semiconductor material and having:
an oxygen scavenged high dielectric constant material formed over the semiconductor material wherein the high dielectric constant material includes reduced oxygen content sufficient to permit an improved capacitive equivalent thickness (CET) of at least 5 Angstroms for the high dielectric constant material.

### Claim 2 (depends on 1)

The device as recited in claim 1, further comprising:
a first electrode formed on the high dielectric constant material; and
a second electrode formed in the semiconductor material.

### Claim 3 (depends on 2)

The device as recited in claim 2, wherein the second electrode includes a diffusion layer in the semiconductor material.

### Claim 4 (depends on 2)

The device as recited in claim 2, wherein the first electrode includes a metal.

### Claim 5 (depends on 1)

The device as recited in claim 1, wherein the semiconductor material includes one of silicon, a III-V material or a II-VI material.

### Claim 6 (depends on 1)

The device as recited in claim 1, wherein the high dielectric constant material includes hafnium.

### Claim 7 (depends on 1)

The device as recited in claim 1, further comprising a passivation layer formed between the semiconductor material and the high dielectric constant material.

### Claim 8 (depends on 1)

The device as recited in claim 1, further comprising a scavenging layer formed on the high dielectric constant material, the scavenging layer being configured to draw out oxygen from the high dielectric constant material.

### Claim 9 (depends on 8)

The device as recited in claim 8, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 10

A device, comprising:
a gate structure including:
a gate dielectric having:
an oxygen scavenged high dielectric constant material formed over a semiconductor substrate wherein the high dielectric constant material includes reduced oxygen content sufficient to permit an improved capacitive equivalent thickness (CET) of at least 5 Angstroms for the high dielectric constant material; and
a gate conductor configured to enable a channel formed in the semiconductor substrate adjacent to the gate structure.

### Claim 11 (depends on 10)

The device as recited in claim 10, wherein the semiconductor substrate includes one of silicon, a III-V material or a II-VI material.

### Claim 12 (depends on 10)

The device as recited in claim 10, wherein the gate conductor includes a metal gate.

### Claim 13 (depends on 10)

The device as recited in claim 10, wherein the high dielectric constant material includes hafnium.

### Claim 14 (depends on 10)

The device as recited in claim 10, further comprising a passivation layer formed between the semiconductor substrate and the high dielectric constant material.

### Claim 15 (depends on 10)

The device as recited in claim 10, wherein the gate conductor includes a scavenging layer formed on the high dielectric constant material, the scavenging layer being configured to draw out oxygen from the high dielectric constant material.

### Claim 16 (depends on 15)

The device as recited in claim 15, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 17

A device, comprising:
a substrate including one of a III-V material or a II-VI material;
a dielectric stack formed over the substrate with improved capacitive equivalent thickness (CET) and equivalent oxide thickness (EOT), having:
an oxygen scavenged passivation layer formed on the substrate; and
an oxygen scavenged high dielectric constant material formed over the passivation layer wherein the passivation layer and the high dielectric constant layer include reduced oxygen content sufficient to permit an improvement of at least 5 Angstroms for CET and EOT; and
a conductive material formed on the high dielectric constant material.

### Claim 18 (depends on 17)

The device as recited in claim 17, wherein the device includes a capacitor and the conductive material forms an electrode of the capacitor, which includes a scavenging layer formed on the high dielectric constant material, the scavenging layer being configured to draw out oxygen from the high dielectric constant material.

### Claim 19 (depends on 18)

The device as recited in claim 18, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 20 (depends on 17)

The device as recited in claim 17, wherein the high dielectric constant material includes hafnium.

### Claim 21 (depends on 17)

The device as recited in claim 17, wherein the passivation layer includes silicon.

### Claim 22 (depends on 17)

The device as recited in claim 17, wherein the conductive material forms a gate conductor, which includes a scavenging layer formed on the high dielectric constant material, the scavenging layer being configured to draw out oxygen from the high dielectric constant material.

### Claim 23 (depends on 22)

The device as recited in claim 22, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 24

A method for fabricating a capacitive component, comprising:
forming a high dielectric constant material over a semiconductor material;
forming a scavenging layer on the high dielectric constant material; and
annealing to form an oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.

### Claim 25 (depends on 24)

The method as recited in claim 24, wherein the semiconductor material includes one of silicon, a III-V material or a II-VI material.

### Claim 26 (depends on 24)

The method as recited in claim 24, wherein forming the high dielectric constant material includes forming the high dielectric constant material using Hafnium.

### Claim 27 (depends on 24)

The method as recited in claim 24, further comprising annealing the high dielectric constant layer before forming the scavenging layer.

### Claim 28 (depends on 24)

The method as recited in claim 24, further comprising forming a passivation layer on the semiconductor material.

### Claim 29 (depends on 24)

The method as recited in claim 24, removing the scavenging layer and the oxide layer.

### Claim 30 (depends on 29)

The method as recited in claim 29, further comprising repeating the formation and removal of the scavenging layer to further reduce oxygen content.

### Claim 31 (depends on 29)

The method as recited in claim 29, wherein a conductive material is formed over the high dielectric constant material.

### Claim 32 (depends on 24)

The method as recited in claim 24, wherein use of the scavenging layer and the oxide layer increases a capacitive equivalent thickness (CET) by at least 5 Angstroms.

### Claim 33 (depends on 24)

The method as recited in claim 24, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 34 (depends on 24)

The method as recited in claim 24, wherein the capacitive component includes one of a capacitor and a gate structure.

### Claim 35

A method for fabricating a capacitive component, comprising:
providing a first capacitive plate formed in a semiconductor substrate;
forming a capacitor dielectric on the substrate with a high dielectric constant material;
forming a scavenging layer on the capacitor dielectric;
annealing to form an oxide layer between the capacitor dielectric and the scavenging layer such that oxygen in the capacitor dielectric is drawn out to reduce oxygen content in the capacitor dielectric;
removing the scavenging layer and the oxide layer; and
forming a second electrode on the capacitor dielectric.

### Claim 36 (depends on 35)

The method as recited in claim 35, wherein the semiconductor substrate includes one of silicon, a III-V material or a II-VI material.

### Claim 37 (depends on 35)

The method as recited in claim 35, further comprising annealing the high dielectric constant layer before forming the scavenging layer.

### Claim 38 (depends on 35)

The method as recited in claim 35, wherein the first capacitive plate includes a diffusion region.

### Claim 39 (depends on 35)

The method as recited in claim 35, further comprising forming a passivation layer on the substrate.

### Claim 40 (depends on 35)

The method as recited in claim 35, further comprising repeating the formation and removal of the scavenging layer to further reduce oxygen content.

### Claim 41 (depends on 35)

The method as recited in claim 35, wherein removing the scavenging layer and the oxide layer increases a capacitive equivalent thickness (CET) by at least 5 Angstroms.

### Claim 42 (depends on 35)

The method as recited in claim 35, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 43

A method for fabricating a capacitive component, comprising:
providing a channel layer in a semiconductor substrate;
forming a gate dielectric over the substrate, which includes a high dielectric constant material;
forming a scavenging layer on the gate dielectric;
annealing to form an oxide layer between the gate dielectric and the scavenging layer such that oxygen in the gate dielectric is drawn out to reduce oxygen content in the gate dielectric;
removing the scavenging layer and the oxide layer; and
forming a gate electrode on the gate dielectric.

### Claim 44 (depends on 43)

The method as recited in claim 43, wherein the semiconductor substrate includes one of silicon, a III-V material or a II-VI material.

### Claim 45 (depends on 43)

The method as recited in claim 43, wherein the scavenging layer includes at least one of aluminum, titanium, silicon and alloys thereof.

### Claim 46 (depends on 43)

The method as recited in claim 43, further comprising repeating the formation and removal of the scavenging layer to further reduce oxygen content.

### Claim 47 (depends on 43)

The method as recited in claim 43, wherein removing the scavenging layer and the oxide layer increases a capacitive equivalent thickness (CET) by at least 5 Angstroms.