# US 8,772,111 B2 · Trench gate semiconductor device and the method of manufacturing the same

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- Number: US 8,772,111 B2
- Document ID: US8772111B2
- Status: Granted
- Kind: B2
- Application number: 13/723,967
- Filed: 2012-12-21
- Published: 2013-05-09
- Granted: 2014-07-08
- Earliest claimed: 2009-12-25
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Yoshihiro Ikura
- Web page: https://patentgrep.com/patent/US8772111B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT.

## Claims

### Claim 1

A method of manufacturing a trench gate semiconductor device, the method comprising the steps of:
(a) forming a first trench from a surface of a semiconductor substrate using an insulator film for a mask;
(b) forming a polysilicon gate electrode in a lower portion of the first trench with a gate insulator film interposed between an inner wall of the first trench and the polysilicon gate electrode;
(c) forming a source region in an upper side wall of the first trench using the insulator film and the polysilicon gate electrode as masks, wherein the source region is formed by oblique ion implantation into the upper sidewall of the first trench;
(d) loading an insulator in an upper portion of the first trench such that an upper surface of the insulator is at a same level with the surface of the semiconductor substrate;
(e) forming a second trench in a surface portion of the semiconductor substrate between the first trenches, the second trench comprising a slanted inner surface extending from a side wall of the first trench to a bottom plane of the second trench positioned lower than a lower end surface of the source region such that the source region is exposed to the slanted inner surface of the second trench;
and
(f) forming a body-contact region of a first conductivity type along the slanted inner surface of the second trench, wherein the body contact region is thinner than the source region.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the source region is formed by a vapor-phase diffusion into the upper sidewall of the first trench.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the source region is formed by a solid-phase diffusion into the upper sidewall of the first trench.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the step (d) comprises the steps of:
depositing the insulator on the semiconductor substrate; and
polishing the insulator with a chemical mechanical polishing apparatus for positioning the upper surface of the insulator at the same level with the surface of the semiconductor substrate.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the second trench is formed by chemical reactive ion etching.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the second trench is formed by anisotropic wet etching.

### Claim 7 (depends on 1)

The method according to claim 1, additionally comprising forming a source electrode on the body contact trench.