# US 8,772,108 B1 · Multi-time programmable non-volatile memory

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- Number: US 8,772,108 B1
- Document ID: US8772108B1
- Status: Granted
- Kind: B1
- Application number: 13/775,844
- Filed: 2013-02-25
- Granted: 2014-07-08
- Earliest claimed: 2013-02-25
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Eng Huat Toh; Shyue Seng Tan; Elgin Quek
- Web page: https://patentgrep.com/patent/US8772108B1

## CPC

- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A process for creating a low-cost multi-time programmable (MTP) non-volatile memory (NVM) and the resulting device are provided. Embodiments include forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region, forming a metal layer over the floating gate, and forming a pair of self-aligned contacts on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.

## Claims

### Claim 1

A method comprising:
forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region;
forming a metal layer over the floating gate; and
forming a pair of self-aligned contacts on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
forming a pair of spacers on opposite sides of the floating gate;
forming a hardmask above the floating gate and between the pair of spacers; and
forming the pair of self-aligned contacts partially covering the hardmask and one spacer of the pair spacers.

### Claim 3 (depends on 2)

The method according to claim 2, comprising:
forming the pair of spacers having rounded corners at top surfaces opposite the hardmask.

### Claim 4 (depends on 2)

The method according to claim 2, comprising:
forming the pair of spacers and the hardmask having co-planar top surfaces.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
forming a second pair of self-aligned contacts on the first and second STI regions, on opposite sides of the doped region, respectively, along a second side of the floating gate across the floating gate from the first pair of self-aligned contacts and electrically connected to the first metal layer.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising:
forming a pair of blocking layers on opposite sides of the floating gate;
forming a hardmask above the floating gate and between the pair of blocking layers; and
forming the first and second self-aligned contacts over the pair of blocking layers and partially covering the hardmask layer.

### Claim 7 (depends on 6)

The method according to claim 6, comprising:
forming the pair of blocking layers of oxide, oxide-nitride-oxide (ONO), or a combination thereof.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
forming a second metal layer over the doped region, the source, and the drain and above the first metal layer; and
forming a bit line contact connecting the second metal layer and the drain.

### Claim 9

A device comprising:
a doped region formed between a source and a drain within a substrate;
first and second shallow trench isolation (STI) regions on opposite sides of the doped region;
a select gate and a floating gate each over the first STI region, the doped region, and the second STI region;
a metal layer over the floating gate; and
a pair of self-aligned contacts formed along one side of the floating gate on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.

### Claim 10 (depends on 9)

The device according to claim 9, further comprising:
a pair of spacers on opposite sides of the floating gate; and
a hardmask above the floating gate and between the pair of spacers,
wherein the pair of self-aligned contacts partially cover the hardmask and one spacer of the pair spacers.

### Claim 11 (depends on 10)

The device according to claim 10, comprising:
the pair of spacers having rounded corners at top surfaces opposite the hardmask layer.

### Claim 12 (depends on 10)

The device according to claim 10, comprising:
top surfaces of the pair of spacers and the hardmask being co-planar.

### Claim 13 (depends on 9)

The device according to claim 9, further comprising:
a second pair of self-aligned contacts formed on the first and second STI regions, on opposite sides of the doped region, respectively, along a second side of the floating gate across the floating gate from the first pair of self-aligned contacts and electrically connected to the first metal layer.

### Claim 14 (depends on 13)

The device according to claim 13, further comprising:
a pair of blocking layers on opposite sides of the floating gate; and
a hardmask above the floating gate and between the pair of blocking layers,
wherein the first and second self-aligned contacts are formed over the pair of blocking layers and partially cover the hardmask layer.

### Claim 15 (depends on 9)

The device according to claim 9, comprising:
the doped region including a P-type channel.

### Claim 16 (depends on 9)

The device according to claim 9, comprising:
the doped region including an N-type channel.

### Claim 17 (depends on 9)

The device according to claim 9, further comprising:
a second metal layer over the doped region, the source, and the drain and above the first metal layer; and
a bit line contact connecting the second metal layer and the drain.

### Claim 18

A method comprising:
forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region;
forming a first metal layer over the floating gate;
forming two pairs of self-aligned contacts on the first and second STI regions, respectively, electrically connected to the first metal layer with self-aligned contacts of each pair being on opposite sides of the floating gate and the two pairs of self-aligned contacts being on opposite sides of the doped region;
forming a second metal layer over the doped region, the source, and the drain and above the first metal layer; and
forming a bit line contact connecting the second metal layer and the drain.

### Claim 19 (depends on 18)

The method according to claim 18, further comprising:
forming a pair of spacers on opposite sides of the floating gate;
forming a hardmask above the floating gate and between the pair of spacers; and
forming each self-aligned contact of the two pairs of self-aligned contacts partially covering the hardmask and one spacer of the pair of spacers.

### Claim 20 (depends on 18)

The method according to claim 18, further comprising:
forming a pair of blocking layers on opposite sides of the floating gate;
forming a hardmask above the floating gate and between the pair of blocking layers; and
forming each self-aligned contact of the two pairs of self-aligned contacts partially covering the hardmask and one blocking layer of the pair of blocking layers.