# US 8,772,107 B2 · Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method for manufacturing nonvolatile semiconductor memory

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- Number: US 8,772,107 B2
- Document ID: US8772107B2
- Status: Granted
- Kind: B2
- Application number: 14/033,886
- Filed: 2013-09-23
- Published: 2014-01-23
- Granted: 2014-07-08
- Earliest claimed: 2010-06-10
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio Masuoka; Hiroki Nakamura
- Web page: https://patentgrep.com/patent/US8772107B2

## CPC

- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate.

## Claims

### Claim 1

A method for manufacturing a nonvolatile semiconductor memory including a plurality of nonvolatile semiconductor memory transistors each including an island-shaped semiconductor having a hard mask in a upper portion thereof,
each of the island-shaped semiconductors having a source region, a channel region, and a drain region in the order of the source region, the channel region, and the drain region from a side of a substrate, a floating gate and a control gate in the vicinity of the channel region in the order of the floating gate and the control gate from a side of the channel region, the method comprising:
forming the island-shaped semiconductors in the substrate;
forming a first source line in the substrate;
forming insulating films on bottom portions of the island-shaped semiconductors and on the first source line;
forming insulating film hard mask sidewalls on outer peripheral walls of the island-shaped semiconductors;
forming a floating gate film on the insulating films and on the insulating film hard mask sidewalls;
forming the floating gates in the vicinity of the channel regions by etching the floating gate film;
exposing a top of the island-shaped semiconductors by etching the insulating film hard mask side walls; and
forming doped regions in the island shaped semiconductors to form the drain regions.

### Claim 2 (depends on 1)

A nonvolatile semiconductor memory comprising the nonvolatile semiconductor memory transistors fabricated according to the method of claim 1,
wherein the plurality of nonvolatile semiconductor memory transistors are arranged in a row direction among row and column directions of the substrate, and
wherein a drain region of at least one of the plurality of nonvolatile semiconductor memory transistors is electrically connected to a second source line extending in a column direction among the row and column directions of the substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein after forming the floating gates and before removing the insulating film hard mask sidewalls, the insulating film hard mask sidewalls cover an upper surface of the floating gates, such that the floating gates reside below the insulating film hard mask sidewalls.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the floating gates in the vicinity of the channel regions by etching the floating gate film further comprises using the insulating film hard mask sidewalls as etching masks.

### Claim 5 (depends on 4)

The method of claim 4, further comprising depositing a control gate film and etching the control gate film using the insulating film hard mask sidewalls as etching masks to form control gates.