# US 8,772,105 B2 · Semiconductor device and method for forming the same

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- Number: US 8,772,105 B2
- Document ID: US8772105B2
- Status: Granted
- Kind: B2
- Application number: 13/211,249
- Filed: 2011-08-16
- Published: 2012-07-05
- Granted: 2014-07-08
- Earliest claimed: 2011-01-03
- Assignees: Hynix Semiconductor Inc.
- Applicants: Tae Su Jang; Min Soo Yoo
- Inventors: Tae Su Jang; Min Soo Yoo
- Web page: https://patentgrep.com/patent/US8772105B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

## Claims

### Claim 1

A method for forming a semiconductor device comprising:
forming a recess by etching a semiconductor substrate;
forming an insulation film over a bottom and a sidewall of the recess;
forming a bit line over the insulation film;
forming a polysilicon layer over the bit line;
forming an undoped amorphous silicon layer over the polysilicon layer, the recess sidewall, and the semiconductor substrate;
forming a crystalline silicon layer by performing solid phase epitaxy on the undoped amorphous silicon layer;
forming a silicon layer over the semiconductor substrate in such a manner that open portions of the recess are filled, the silicon layer being formed by performing a selective epitaxial growth method using the crystalline silicon layer as a seed;
forming a first junction region in a bottom portion of the silicon layer by implanting ions in the silicon layer; and
forming a pillar by etching the silicon layer, the first junction region and an interlayer insulation film.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the forming the recess includes:
forming an oxide film and a hard mask pattern over the semiconductor substrate; and
etching the oxide film and the semiconductor substrate using the hard mask pattern as an etch mask.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the recess has a depth of 50 nm to 300 nm.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
performing an annealing process including H2.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the forming the insulation film over the bottom and sidewall of the recess includes:
forming an insulation material over the semiconductor substrate to cover exposed surfaces of the recess; and
performing an etchback process on the insulation material.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising:
forming a barrier conductive layer between the bit line and the polysilicon layer.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising:
forming an amorphous silicon layer over the bit line.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
exposing a surface of the semiconductor substrate and an upper portion of the recess sidewall.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the exposing the surface of the semiconductor substrate and the upper portion of the recess sidewall includes:
performing ion implantation on an oxide film and the insulation film; and
removing the ion-implanted oxide film and the ion-implanted insulation film by performing a cleaning process.

### Claim 10 (depends on 9)

The method according to claim 9, further comprising:
after exposing the surface of the semiconductor substrate and the upper portion of the recess sidewall,
performing heat treatment at a temperature of 200° C. to 1000° C. in an H2 atmosphere for 10 to 120 minutes.

### Claim 11 (depends on 1)

The method according to claim 1, further comprising:
performing a heat treatment process affecting a portion of the semiconductor between the bit line and the polysilicon layer disposed over the bit line, thereby forming silicide.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the heat treatment process is performed at a temperature of 300° C. to 800° C. in an N2 atmosphere for 1 to 60 minutes.

### Claim 13 (depends on 1)

The method according to claim 1, further comprising:
performing a planarization etching process on the silicon layer.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the forming the first junction region includes:
implanting N-type ions or P-type ions, wherein the N-type ions include phosphorus (Ph) or arsenic (As) and the P-type ions include boron (B).

### Claim 15 (depends on 1)

The method according to claim 1, wherein the forming the first junction region is performed under process conditions including a dose of 1E10/cm2 to 1E18/cm2 and energy of 1 KeV to 200 KeV.

### Claim 16 (depends on 1)

The method according to claim 1, further comprising:
forming a gate oxide film over a sidewall of the pillar;
forming a gate over the gate oxide film; and
forming a second junction region in an upper portion of the pillar.

### Claim 17

A method for forming a semiconductor device comprising:
forming a recess by etching a semiconductor substrate;
forming an insulation film over a bottom and a sidewall of the recess;
forming a bit line over the insulation film;
exposing a surface of the semiconductor substrate and an upper portion of the recess sidewall;
forming a silicon layer over the semiconductor substrate in such a manner that open portions of the recess are filled;
forming a first junction region in a bottom portion of the silicon layer by implanting ions in the silicon layer; and
forming a pillar by etching the silicon layer, the first junction region and an interlayer insulation film,
wherein the exposing the surface of the semiconductor substrate and the upper portion of the recess sidewall includes:
performing ion implantation on an oxide film and the insulation film; and
removing the ion-implanted oxide film and the ion-implanted insulation film by performing a cleaning process.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising:
forming an undoped amorphous silicon layer over a polysilicon layer, the recess sidewall, and the semiconductor substrate;
forming a crystalline silicon layer by performing solid phase epitaxy on the undoped amorphous silicon layer; and
forming the silicon layer by performing a selective epitaxial growth method using the crystalline silicon layer as a seed.

### Claim 19 (depends on 17)

The method according to claim 17, further comprising:
after exposing the surface of the semiconductor substrate and the upper portion of the recess sidewall,
performing heat treatment at a temperature of 200° C. to 1000° C. in an H2 atmosphere for 10 to 120 minutes.