# US 8,772,103 B2 · Low temperature implant scheme to improve BJT current gain

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- Number: US 8,772,103 B2
- Document ID: US8772103B2
- Status: Granted
- Kind: B2
- Application number: 13/246,362
- Filed: 2011-09-27
- Published: 2012-04-26
- Granted: 2014-07-08
- Earliest claimed: 2010-10-25
- Assignees: Texas Instruments Incorporated
- Applicants: Ming-Yeh Chuang
- Inventors: Ming-Yeh Chuang
- Web page: https://patentgrep.com/patent/US8772103B2

## CPC

- H10P 30/226: {at a temperature lower than room temperature}
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region.

## Claims

### Claim 1

A process of forming an integrated circuit containing a pnp BJT and a p-channel metal oxide semiconductor (PMOS) transistor, comprising:
forming a implant screen dielectric layer over a top surface of a silicon top region of a substrate of said integrated circuit, over an emitter region of said pnp BJT and source and drain regions of said PMOS transistor;
forming an implant mask over said implant screen dielectric layer so as to expose said emitter region and said source and drain regions;
bringing said substrate of said integrated circuit in contact with a substrate chuck;
cooling said substrate chuck so that said substrate of said integrated circuit is cooled to a temperature of 5° C. or colder; and
while said substrate is cooled to 5° C. or cooler, ion implanting p-type dopants concurrently into said emitter region and said source and drain regions, in which said p-type dopants and a dose of said p-type dopants are selected from the group consisting of
boron at a dose of at least 1×1016 atoms/cm2,
gallium at a dose of at least 7×1013 atoms/cm2,
indium at a dose of at least 6×1013 atoms/cm2, and
any combination thereof.

### Claim 2 (depends on 1)

The process of claim 1, in which said implant screen dielectric layer includes at least 80 percent silicon dioxide.

### Claim 3 (depends on 1)

The process of claim 1, in which said implant screen dielectric layer is at least 15 nanometers thick.

### Claim 4 (depends on 1)

The process of claim 1, in which said implant mask is formed of photoresist.

### Claim 5 (depends on 1)

The process of claim 1, in which said step of ion implanting said p-type dopants amorphizes silicon material at said top surface of said silicon top region in said emitter region and said source and drain regions to a depth of at least 15 nanometers.

### Claim 6 (depends on 1)

The process of claim 1, in which said step of cooling said substrate chuck is performed by flowing a coolant fluid through said substrate chuck.